R CONVERTER BASED PCU, TO CONFIRM THE FLEXIBILITY AND PERFORMANCE OF THE CONVERTER TOPOLOGY

The main objective of this activity was to study the BR converter [1] and to confirm its flexibility and performance (mainly efficiency and mass reduction) versus solutions that is implemented in a satellite PCU. For details see [2] ESTEC SOW. An architecture with centralised regulated bus, single battery and centralised solar array was selected for this study. Project Plan: Study, design and development of an evaluation prototype, based on the B3R topology (including protections and control loops). Study, design and development of an Electrical Elegant Breadboard including three power stages, based on the B3R topology (including protections and control loops). Laboratory tests of these converters (power stages, control loops and protections). Conclude the study by comparing the achieved performances (including efficiency and mass) versus current solutions implemented on a satellite PCU. Summary of the pros and cons of the use of the BR concept.


INTRODUCTION
In a satellite, the main function of a Power Conditioning Unit (PCU) is to manage the energy coming from several power sources (usually solar arrays and battery) and to deliver it continuously to the users in an appropriate form during the overall mission. The ESA Power Conditioning Department proposed new solutions based on Buck Buck Boost Regulators (B³R), which appeared to be a promising alternative [1]. They predicted on one hand more efficient regulators and or on the other hand a better utilisation of the source, since they are capable of operating on a wider range of source characteristics. This new B³R topology is a multiple port DC DC converter, which can interface a solar array, a battery and generate a regulated DC bus voltage. The B 3 R topology is a flexible topology that can be used in different architectures for different applications.
For this study different architectures of the solar array (centralised or distributed), the regulated bus (centralised or multiple) and the battery (single or segregated) were discovered. After a comparison of properties, the architecture "Centralised Regulated Bus and Single Battery and Centralised Solar Array" was selected.

Figure 1-1: Centralised Regulated Bus and Single
Battery and Centralised Solar Array

STUDY LOGIC
The objective of this task was to design and build an Electrical Elegant Breadboard to study the adequacy of the protections and evaluate the stage performances at B³R level and at architecture level. According to the selected architecture an Electrical Elegant Breadboard (EEBB) of the single point failure free architecture was designed. Since the design was suitable the Agency decided to approve it. The power architecture contains three B³R power stages with their dedicated current control loops and protections. The higher level control loops are located on a separate printed circuit board.
For the purpose of the study it was found as adequate to manufacture the Electrical Elegant Breadboard with commercial EEE parts, having same or equivalent functionalities and performances as Hi-Rel EEE-parts..

DESIGN DESCRIPTION
The EEBB is built up on two circuit boards and one mechanical frame. One board is the Power Board (blue in Fig. 3-1). It includes three B 3 R power stages. The Controller Board (green in Fig 3-

Protection
Every B 3 R power stage protection has an independent circuit which monitors several signals. Three MOSFET switches are controlled by the protection to isolate the power stage in case of a detected failure (battery protection switch, solar array protection switch and protection switch against short circuit to ground).  The switches are controlled by a central latch. When an over load condition is detected, the latch is set, the power stage is disabled and the protection switches opens. The latch stays active until a power cycle occurs (SA and Battery disconnect and reconnect) or an external RESET command is issued. Fig. 3-1 shows the possible sources to set and reset the latch, and the state of the protection switches and the power stage.

Battery Output Over Current
A segregated current sense amplifier is connected to the shunt resistor in the battery port output. If the charge current to the battery exceeds the limit, the protection will be triggered. This threshold is set around to 14A, which is well above the maximum current that the control circuit in normal operation will permit (10A). Buck and boost PWM signals are disabled when the protections trigger.

Battery Output Uncommanded Current
The current sensed by the battery over current protection is used to detect uncommanded current to the battery. The current command signal from the controller  14009 (2017 ) board is used to detect a zero current command. If a zero current command is detected and there is still current flowing on the battery port, the protection will be triggered. The threshold to detect uncommanded current is 0,5A.

Bus Output Over Current
A segregated current sense amplifier is connected to the shunt resistor in the battery port output. If the charge current to the battery exceeds the limit, the protection will be triggered. This threshold is set around to 9A, which is well above the maximum current that the control circuit in normal operation will permit (7,6A). Buck PWM signals are disabled when the protection trigger.

Bus Output Uncommanded Current
The current sensed by the bus over current protection is used to detect uncommanded current to the bus. The current command signal from the controller board is used to detect a zero current command. If a zero current command is detected and there is still current flowing on the bus port, the protection will be triggered. The threshold to detect uncommanded current is 0,5A.

Protection Switch Voltage Drop
In normal operation, the voltage drop on all three protection switches is monitored. The voltage drop is caused by the RDSon and the current of the protection switch. If a protection switch fails in a way that increases RDSon, the voltage drop will also increase. A voltage drop over 0,7V will trigger the protection latch.

Over Current to Ground
In the normal operating the current through Ground can flow in both directions. This depends on the operating condition. In a failure case, the current flows to ground. To protect from a short circuit to ground in any point of the power stage, the current to ground is sensed. If the current increases over the threshold, the protection will trigger.

SA Input Over-Current
The SA input current will be measured using the voltage drop over the input filter inductor. If the current increases the max input current threshold, the protection will trigger. Fig. 3-5 shows the connection principle between the different power stages. The SA input current will be measured using the voltage drop over the input filter inductor. The current is compared to the input current of another power stage. In normal operation all B3R power stages get a common current output command. Therefore the output currents are identical. Then also the input currents are identical. If one power stage suffer a failure which increase the power dissipation of that converter, the input current will increase to maintain the commanded output current. This will be detected by the SA input current mismatch monitor and triggers the protection latch. This monitor is combined with the input over current protection. The threshold to activate the protection is either the max input current, or a reduced level transmitted from another power stage. The power stage itself transmits its input current level to the next power stage for comparison. To avoid unintended trigger of that monitor, a current level will only be transmitted if the power stage operates in normal conditions. An activation of the protection latch or an internal supply failure disables the transmission of the input current level to the next stage.

Solar Array Short Circuit Protection
In addition, there are several input protection switches connected in the return line of the solar array that will isolate shorted strings of the solar array avoiding losing the whole section or solar array. As a baseline, 3 switches (MFETs) per B3R are implemented. If a failure in the solar array side, for example in the driving mechanism, leads to a short circuit of it, and all the sections are directly connected together, as happens to be in a centralised solar array, the whole solar array  (2017 ) will be lost. However, if the solar array is divided in sections, each one connected through a protection switch, in case one fails, only that section will be lost, minimising in this way the risk.

Control Scheme and MPP Tracking
The control of the PCU is implemented with different control loops.
-Basic current control loops on the power stage -High level control loops on the controller board

Basic Current Control Loops
The basic current control loops are located on the B 3 R power board and regulates the output current of the battery port and the bus port. Fig. 3-6 shows the two basic current control loops which get the current command from the high level controller fitted on the control board. These basic current control loops are implemented on each B 3 R power stage. This arrangement ensures equivalent current sharing over the different power stages. The output of the current controllers is feed to a voltage comparator. It is compared to a saw tooth signal to generate a PWM signal which drives the power stage. To insure proper start up the controller is initialised by the protection latch. With an active protection signal, the integrator of the controller is held in reset state. When the converter gets enabled (power up or enable command) the controller does a soft start.

High Level control loops and MPP Tracking
The high level controller generates the current command for the basic control loops. These current command signals are global signals for all B 3 R power stages. To reach the required system availability they have to be single point failure free. Therefore these signals are generated by majority voted outputs of the triplex controllers.

Bus Output Voltage Controller
The bus voltage controller is a Type III compensator. It provides three poles and two zeros, which are selected to reach the desired gain and phase margin. The compensator is implemented three times with a following majority voter. The voted output is the current command for the bus output and is distributed to all converters. See Fig. 3-7.

End of charge control Loop
This loop control limits the maximum battery charge voltage and current. It contains two compensators. One is a type II compensator to control the battery charge voltage, the other is a type I compensator which controls the max charge current. The schema is shown in Fig. 3-7, Battery Management. The battery voltage controller has a max voltage reference which can be reduced by the max charge current controller. This arrangement ensures compliance with the battery operating limitations. The output of the battery management controller is linked together with the output of the MPPT. The lowest current command will generate the current command for the battery output.

MPP Tracking
The maximum power point tracker uses the "perturb and observe" method to find and track the maximum power point. Three independent trackers generate a voted SA voltage reference. A SA voltage controller uses this reference to generate a battery output current command. See Fig. 3-7 for the schema. The SA voltage controller is implemented with a type II compensator which provides two poles and one zero. They are positioned in a way to reach the desired phase and gain margin.

TEST RESULTS
The B3R

Efficiency
Efficiency was measured on the connectors of the EEBB and based on one power stage. It includes all internal B3R losses like the cooper tracks, filter inductors, protection switches and current sense shunts, auxiliary power supply and the power stage. The following figures show the efficiency for different operating modes with different load and charge current. The X-axis shows the battery port current. Negative current means battery discharging. The Y-axis shows the bus current.

Stability Of The Control Loops
In battery charging mode, the MPPT ensures always operating in MPP. If the charging voltage of the battery is reached, the power, delivered by the SA, has to be reduced. There are two different regions to operate the SA, to reduce the power of the SA: Current region and voltage region.

Stability EOC In Voltage Region
To operate the EOC in the voltage region of the SA, the current control loop is configured to operate in voltage region. Therefore the pulse wide of the power switches will be reduced, when a lower output current is demanded. Zero current demand cause the buck and boost switches to open, leading to the maximum no load voltage of the SA. All loops were measured and analysed.
The current loops were measured in boost and buck operation and reach all a phase margin > 60° and gain margin > 10 dB with a bandwidth > 17 kHz.
The input voltage loops result where measured in buck and boost operation and reach all a phase margin > 56°a nd gain margin > 10 dB with a bandwidth > 1,6 kHz.

Stability EOC In Current Region
To operate the EOC in the current region of the SA, the current control loop is configured to operate in current region. Therefore the pulse wide of the power switches will be increased, when a lower output current is demanded. Zero current demand cause the buck and boost switches to close, leading to the maximum short current of the SA. All loops were measured and analysed.
The current loops were measured in boost and buck operation and reach all a phase margin > 60° and gain margin > 10 dB with a bandwidth > 400 Hz.
The input voltage loops result where measured in buck and boost operation and reach all a phase margin > 49°a nd gain margin > 11 dB with a bandwidth > 1 kHz. The result shows stable operation in every condition. The bandwidth is much lower compared to operating in  (2017 ) the voltage mode. Further investigation showed the limiting factor is the capacitance on the SA input. In the current region, the SA behaves as a current source for low frequencies (high impedance). As frequency increase the SA behaviour turns to a voltage source (low impedance).

Internal Failures Stimulation
To verify the detection of power component failures all cases, which are identified to be critical, were stimulated by HW failure injection. The critical failure cases where identified by analysis and simulation and a result of the FMECA. All tests where done in the following way: -Applying the failure during normal operation and record the reaction. -With the failure still applied, enable the converter by an enable command and verify the reaction of the protection. -Remove the failure stimulation and enable the converter by an enable command.

EEBB HARDWARE
Picture 3 shows the EEBB hardware. The three power stages can be identified on the power board mounted in the frame within three vertical sections. The Controller Board is assembled above the Power Board.

SUMMARY OF THE STUDY RESULTS
As a result of this activity, it was shown that a flexible PCU with several B³R power stages can be implemented. For the comparison with current implementations the following key parameters were determined: -SA input voltage: 0 -60V -Battery Voltage: 32 -50V -Regulated Bus Voltage: 28V -Maximum solar array input power of one power stage: 600W -Efficiency in buck mode, including supply and protections: 93% max. -Efficiency in boost mode, including supply and protections: 91% max. -Weight-Power ration in a two out of three operating condition: 1.725g/W (worst case) -Weight-Power ration in a five out of six operating condition: 1.38g/W A PCU implementation of a single point failure tolerant B³R topology was successfully demonstrated. In a primary PCU, single point failure tolerance is essential for the operation in a spacecraft. It was found as important to detect and isolate failures in the power stage. This ensures that after a failure case neither the Solar Array, the Battery and the Bus ports are shorted, nor significant power dissipation will propagate heat and damage redundant power stages. Detailed analysis and tests with stimulated power components failures where done and showed a reliable detection and isolation of the affected power stage.
Operating during end of charge (EOC) in the current or voltage region of the Solar Array was tested. It was shown that both operation modes are feasible with different characteristics. Also it was shown, that the B 3 R is able to handle abnormal conditions, like start up from depleted battery.