Non-isolated Modified Quadratic Boost Converter with Midpoint Output for Solar Photovoltaic Applications

. This paper presents a boost DC-DC converter topology with non - isolated high gain and output midpoint, to boost the voltage obtained from solar photovoltaic panels. The three-level boost converter is coupled to the output port of the single-switch quadratic boost converter to derive the proposed converter topology. The voltage gain of the proposed converter is greater than that of the classical boost converter. The voltage stress on the switches of the proposed converter is equal to half of the converter output voltage. Static analysis, operating modes, experimental waveforms in continuous current conduction and discontinuous current conduction modes are shown. A 520 W prototype converter was implemented in the laboratory and its results are presented.


Introduction
In photovoltaic systems with multiple modules connected in series, partial shadowing can lead to a reduction of voltage and power available from the panels together. In addition, the tracking of maximum power point is complex because the system has multiple peaks, resulting from the local maximum power points. In [1,2] a comparative investigation of various photovoltaic arrangements with partial shading is presented. Still, the power of a photovoltaic panel is between 100 W and 350 W, and the voltage at maximum power point is 12 V to 42 V. The above values are not sufficient when compared to the voltage required in the dc bus of inverters, which reduces the efficiency of the whole system [3,4].
To extend the conversion range, the cascaded boost converters was used [5,6]. However, the resulting structure is large and control is complex. With simplified structure, the quadratic boost converter with a single switch was proposed and analysed in [7][8][9], and in [9,10] the drive cell has been associated to aid self-resonant switching, allowing the zero-voltage switching in the converter switch. The voltage gain can be increased by using magnetic coupling, coupled inductors based high gain converters are introduced in [11,12]. With this technique, the ripples in the inductor current and the reverse recovery problems in the diodes are reduced. However, the voltage stress of the output diode is still high, the leakage inductance and parasitic capacitor of the diode will form a resonant circuit. Additionally, the ripples in the input current is highly discontinuous. By switched -capacitor technique, the topologies proposed in [13,14] provide increased gain, but this can be achieved by using large number of capacitors.
The conduction and switching losses of quadratic converters are significant, making these converters more suitable for low power applications. Using three-state cells, high-gain converters with reduced input current ripple was proposed in [15,16]. The solution presents a high gain, where the gain is increased by increasing the turns-ratio of the coupled inductor. A converter topology utilizing three-state cell and voltage multiplier cell was proposed in [17]. This solution may be limited to high power applications as a function of the current flowing through the capacitors. The voltage stresses in the semiconductor devices can be reduced as in [18], where the maximum voltage applied to the switches are equal to the fraction of its converter output voltage. The topology proposed in [19] presents asymmetry in the voltages across the switches when the gain is greater than 4, being characterized as a disadvantage despite the converter can operate with gains higher than four. Other quadratic converter topologies were presented in [20,21], for driving the Light Emitting Diode, but the step-down voltage version. Besides these applications, a quadratic converter was used as a battery charger in [22]. In this case the system was developed to contemplate a high power-factor. With high voltage gain and low input current ripple, a converter topology based on interleaving technique was proposed in [23]. This article proposes a new topology for high gain DC-DC converter based on quadratic feature, which use low voltage switch and access to the midpoint of the output voltage.
The proposed converter topology is devised by connecting the three-level boost cell [24] shown in Fig. 1 (a) to the output port of the quadratic boost converters [5][6][7] which is shown in Fig. 1 (b). The resultant proposed converter is shown in Fig. 2. Use In the proposed topology, an appropriate modulation strategy was adopted and the output capacitors are equal, Co1 = Co2, hence the voltage on these capacitors will be half of total output voltage of converter. The switches, S1 and S2 are clamped at half of output voltage, thus a significant reduction in voltage stress on switches. In contrast, current flowing through the switches are the sum of the currents of inductors, L1 and L2. The switching technique used for operating the proposed converter is a delayed modulation technique, implemented through two 180° lagged pulses with fixed frequency and variable duty ratio. The converter will have two distinct regions of operation, the first relating to operation where duty cycle is lesser than 0.5 and other with a duty cycle greater than 0.5. The control signals of the switches can be seen in Fig. 4 and Fig. 6.

Principle of operation
To understand the proposed converter operation, the analysis is made for Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operations and the converter is investigated in the two regions defined by the duty cycle ratios.

Operation in CCM
The operating modes in CCM for duty ratio less than 0.5 are described below. The four operating modes of proposed converter for D < 0.5 is shown in Fig. 3. The theoretical waveforms related to these modes are shown in Fig. 5.
First step of operation (t0 -t1) -( Fig. 3 (a)): Switches, S1 and S2 are in off state and the inductor current decreases linearly. While the Coint capacitor and the inductor L1 are being charged from the input power source, the inductor L2 and the capacitors Co1 and Co2 supply power to the load.
Second step of operation (t1 -t2) -( Fig. 3 (b)): In this step of operation, S1 remains in off state and S2 is switched on. The energies from the input source and inductors are transferred to both the capacitor Co1 and the load.
Third step of operation (t 2 -t 3 ) -( Fig. 3 (a)): This step of operation begins when S2 is turned off. The topological structure and the operation of this step are similar to the first step of operation.
Fourth step of operation (t 3 -t 4 ) - (Fig. 3 (c)): During this step of operation, switch S1 is turned on and the switch S2 remains in off state. The energy is transferred to the capacitor Co2 and load from the input source. From the theoretical waveforms which was shown in Fig. 4, for D < 0.5, the equations for time intervals in terms of duty cycle, D and time period, T are given in (1) and (2).
The voltage gain of the proposed converter in Continuous Conduction Mode for duty cycle less than 0.5 can be obtained by determining the average voltage in inductors L1 and L2 during one full cycle of operation. Since this converter is composed of two conversion stages, static gain analysis can be done individually.
At steady state, the average inductor voltage across L1 is equal to zero, as given by (3), where Vin is the input voltage; Voint is the intermediate voltage and Vo is the output voltage. The partial voltage gain of the first step of operation is calculated and given in (4).
In the same way, the partial voltage gain is determined for the second step of operation, and it is given in equations (5) and (6). Multiplying the partial voltage gains (4) and (6), which gives equation (7), the total voltage-gain of the proposed converter in continuous conduction mode for D < 0.5.
The converter operating in CCM for duty cycle greater than 0.5 is described below. Fig. 4 illustrates the different operation steps and Fig. 6 shows the key waveforms of the proposed converter. First step of operation (t0 -t1) -( Fig. 4 (a)): Switches, S1 and S2 are in conduction state and the inductor current increases linearly. At this stage of operation, there is no energy transfer between the source and the load. The load is being powered by capacitors Co1 and Co2.
Second step of operation (t1 -t2) -( Fig. 4 (b)): The second operating step starts when the switch, S2 is switched off and diodes D 1 and D 4 are in conducting state. The capacitor Coint is being charged from the supply voltage Vin and the energy from inductor, L1. The inductor L2 transfers its energy to the capacitor Co2. Third step of operation (t2 -t3) -( Fig. 4 (a)): This step begins when S2 is turned on again. The topological condition and operation of this step are the same as the first step of operation.
Fourth step of operation (t3 -t4) - (Fig. 4 (c)): When the switch, S1 is turned off, the fourth step of converter operation starts. However, switch, S2 continues its conduction process. During this operation, the power from input source, energy from L1, charge across Coint and energy of the inductor L2 deliver energy to the capacitor Co1. The waveforms shown in Fig. 6 is used to determine the equations of the time intervals of the four operating steps in terms of time period and duty cycle and they are given in equations (8)   3 zero. Thus, the expression can be written as in (10). The partial voltage gain of the proposed converter in first operating step is given by the relationship between V in and Voint. It is determined by (11). In steady state, the average voltage across inductor, L2 equals zero, as shown in (12). Equation (12) gives equation (13), which is the partial voltage gain of the proposed converter in its second operating step. The partial voltage gains which are given in equations (11) and (13) are multiplied to determine the total voltage gain of the proposed converter in continuous conduction mode for duty cycle more than 0.5 and it is given in (14). Fig. 7 demonstrates the voltage gain of classic boost converter, basic quadratic boost converter and the proposed converter, all operating in the continuous conduction mode. It is observed from the figure that the voltage gain of the proposed converter is always greater than (or equal at D = 0.5) the gain of the classic boost converter. In this way, one can obtain higher voltages from a lower voltage, without using larger duty cycles, which results in reduction of power losses in the semiconductor devices.
For a given current ripple specifications, it is possible to obtain the value of inductances L1 and L2, for both the duty cycle less than 0.5 and greater than 0.5, and it is given in equations (15) to (18). The equations of the current ripple in the inductor L1 can be normalized by dividing (15) and (17) by the input current of the converter. The input current is related to output current, which results in (19) and (20). Thus, we have (21) and (23), where Ro represents load resistance. The current ripple of inductor L2 has been normalized by dividing (16) and (18) by the output current of converter, which results in equations (22) and (24).

Operation in DCM
In the discontinuous conduction mode, three possible discontinuities occur in the proposed converter operation. The first two possibilities are identified by the discontinuity of current in the inductor L1 or current in the inductor L2. While the third possibility is indicated by the discontinuity of currents flowing in both L1 and L2. The first two possibilities will be called as first Partial 4 Discontinuous Conduction Mode (PDCM) and the third possibility will be called as Total Discontinuous Conduction Mode (TDCM). However, considering that the mean current of L1 is greater than the mean current of L2 and if the current ripple in both inductors are equal, then the current flowing in inductor L2 always cancels the current flowing in the inductor L 1 . Thus, in this work, the PDCM operation refers to the current discontinuity only in the inductor L2. The analysis for the PDCM is presented for the two operating conditions defined by the duty cycle (for D < 0.5 and for D > 0.5). The six operating steps of the proposed converter in the PDCM for the duty cycle less than 0.5 are explained below. The circuit diagrams of the converter for different operation steps and the theoretical waveforms of the proposed converter are shown in Fig. 9 and Fig. 10. First operation step (t0 -t1) - (Fig. 3 (a)): The switches, S1 and S2 remain in off state and the inductor current decreases linearly. While the source Vin and L1 send energy to Coint, the inductor L2 and the capacitors Co1 and Co2 feed energy to the load.
Second operation step (t1 -t2) - (Fig. 9): This operation step starts when the current of L2 reaches zero, blocking D3 and D4. In this step, the Coint capacitor continues to be charged with the energy of Vin and L1, however the load is fed by the capacitors Co1 and Co2.
Third operation step (t2 -t3) - (Fig. 3 (b)): When the switch S2 is turned on and switch S1 remains in off state, this third step of operation starts. The current flowing through the inductors L1 and L2 increases linearly, and energy is transferred to Co1 and the load.
Fourth operation step (t3 -t4) - (Fig. 3 (a)): During this operation step, switches S 1 and S 2 are in off state. The topological condition and operation of this step are the same as first mode. Fifth operation step (t2 -t3) - (Fig. 9): This mode of operation starts, when the L2 current reaches zero. The topological condition and operation of this step are the same as the second step of operation.
Sixth operation step (t3 -t4) - (Fig. 3 (c)): In this operation step, the switch S1 is turned on, and switch S2 remains in off state. During this operating mode, current flowing through the inductors L1 and L2 increase again. The capacitor Co2 and the load receives the energy from the inductors.
The six converter operating steps in PDCM for duty cycle greater than 0.5 are described below. The converter operating modes and the theoretical waveforms are shown in Fig. 11 and Fig. 12.
First step of operation (t0 -t1) -( Fig. 5 (a)): In this mode of operation, the switched S1 and S2 are in conducting state and the current flowing through the inductors increases linearly. D1, D3 and D4 are in off state. The load is being powered by the capacitors Co1 and Co2.
Second operation stage (t1 -t2) -( Fig. 5 (b)): In this operating step S1 remains conducting and S2 is turned off. The currents in the inductors decrease linearly. The source Vin and inductor L1 transfers the energy to Coint, however L2 transfers the energy to Co2 and load.
Third operation step (t2 -t3) -( Fig. 11 (a)): This stage begins when the L2 current reaches zero, reverse biasing D3 and D4. The supply voltage Vin and the inductor L1 charges C oint continues to charge with the energy obtained from Vin and L1, and the load is fed by the capacitors Co1 and Co2.
Fourth operation phase (t3 -t4) - (Fig. 5 (a)): this operation mode starts when S2 is turned on again. In this step, the inductors store energy and capacitors Co1 and Co2 feed the load. Fifth stage operation (t4 -t5) - (Fig. 5 (c)): When the switch S1 is turned off, the converter shifts to this operating mode. In this mode, the source Vin and L1 charge the capacitor Coint, while the inductor L2 delivers the energy to Co1 and the load.
Sixth stage operation (t5 -t6) -( Fig. 11 (b)): This mode occurs when the current in L2 reaches zero, and the diode D3 is reverse biased. The topological state and operation of this step are similar to the third step.
Based on the converter operating mode waveforms shown in Fig. 10 and Fig. 12, the mean values of the voltages in the inductors L1 and L2 are calculated, we obtain (27) and (28), which gives the equations for the total voltage gain of the proposed converter in partial discontinuous conduction mode. The parameter γ2 is a current parameter which represents the external factors that influence the static behaviour of the converter.

Experimental results
A laboratory prototype of the proposed converter with a power rating of 520 W was built in order to demonstrate its operation and performance. The parameters used to design the proposed converter is given in Table 1. The power rating and rated voltage values are equal to an array of four solar photovoltaic panels, each having 130W and 17 V at maximum power. The switching frequency was chosen with the purpose of comparing the constructive aspects of this converter with the work carried out in [19]. The design parameters of the inductors and the capacitors presented in the proposed converter were calculated by considering the duty cycle, D = 0.79. The maximum current ripples of the inductors were limited to 20% of the mean value of the current in each inductor. The voltage ripples on the capacitors were limited to 1% of the mean voltage on the respective capacitor.  Switching frequency, f 50 kHz Fig. 13 shows the experimental waveforms of the proposed converter. The input voltage is 34 V and the mean current flowing through the inductor is 15.38 A with ripple of 9 %, which is allowable as shown in Fig. 13 (a). The intermediate voltage across the capacitor is almost 80 V and the mean current flowing through the inductor L2 is 6.47 A, with ripple of 12 % as shown in Fig. 13 (b). The voltage stress across the switches S1 and S2 and maximum reverse blocking voltage across the diodes D3 and D4 are 190 V, which is equal to half of the total output voltage of the converter as shown in Fig. 13 (c) and 13 (d). The proposed converter has midpoint in the output port, so that the inverter can be directly connected to it without using any extra components. The voltage across each output capacitor is equal to 190 V as shown in Fig. 13 (e). The output voltage and current of the proposed converter for given specification is shown in Fig. 13 (f), and they are 380 V and 1.37 A, respectively. Fig. 14 shows the efficiency curve of the converter as a function of output power. The efficiency reaches its maximum value at the output power of 350W. Although the efficiency value is low when compared to other single-stage and highvoltage converters, similar results were found in other high gain and low input voltage converters.