A New Dynamic Voltage Restorer with Multi-level Open-end Winding Topology

In this paper, a variety of main circuit structures of DVR based on open-end winding are presented. Two inverters are connected in series to realize the multi-level structure and simplify the hardware cost. According to the mathematical model of open-end DVR, a three loop control strategy based on load voltage feedback is implemented to suppress the resonance of LCL filter. Aiming at the common mode voltage problem of open-end winding DVR, a common mode voltage suppression strategy based SVPWM is proposed to completely suppress the common mode voltage of high frequency and low frequency of the system. Finally, an open-end DVR experimental platform is built to verify the effectiveness of the control strategy and modulation strategy.


Introduction
Power quality problems widely exist in petrochemical industry, power system, metallurgy and steel, electrified railway, urban construction and other industries, mainly caused by various asynchronous motors, transformers, thyristor converters, frequency converters and other equipment. Dynamic voltage restorer (DVR) can realize the voltage stability of the sensitive load side, so it becomes an effective solution for voltage sag and flash. When the grid voltage suddenly changes, DVR injects the series compensation voltage with controllable amplitude and phase to the distribution line, so as to realize the constant load voltage [1,2].
DVR is connected to power grid and load in series by transformer. Several typical DVR topologies are proposed in literature [3][4]. The widely used three-phase three leg or three-phase four leg two level converter or the multi-level Clamped converter used in high-power occasions. In the last century, Isao Takahashi, a Japanese scholar, put forward the concept of open-end winding for the first time: the topology of opening the neutral point of the stator winding of the motor and supplying power from both ends of the winding by two-level converters [5,6], which can be equivalent to a NPC topology outputting three-level phase voltage. In DVR, the contacts on both sides of the primary side of the transformer are connected in series between the grid and the load, while the contacts on both sides of the secondary side can be connected in series to the converter, forming an open-end winding topology. Compared with the traditional three-level converter, it optimizes the hardware structure and omits the clamp diode. Through the series connection of the converter, it can improve the utilization ratio of DC voltage. The open-end topology can also reduce the value of DC voltage under the condition of compensating the same network voltage amplitude, which is more conducive to the design of DC side energy storage unit or super capacitor.
There are many different forms of open-end winding series structure. Different topologies can be selected for DVR specific application scenarios. In this paper, the open-end winding DVR structure is taken as the research object. Firstly, the topological structures of different open-end winding structures are given, and the suitable application scenarios of each structure are defined. The three loops control strategy of load voltage, inductance current and compensation voltage is realized. Based on the two-level open-end winding structure, the modulation strategy of common mode voltage suppression is completed. Finally, the effectiveness of topology and control strategy is verified by experiments.    Fig. 1 (a) (b) shows two level open-end winning of the common DC bus and two level open-end winning of the independent DC bus. In the low-voltage application scenario, using two-level series structure can not only ensure the effective compensation of load voltage, but also be equivalent to three-level structure to reduce the harmonic content of compensation voltage. The advantage of the common DC bus is to reduce a group of DC sources, and the energy storage battery can be controlled centrally. However, the disadvantage of common DC is that it needs the common mode voltage suppression, which can reduce the utilization of DC voltage. Under the condition of compensating the same voltage, the common DC structure needs to raise the DC voltage. Fig. 1 (c) (d) shows three level open-end winning of the independent DC bus and three level open-end winning of the common DC bus. In some medium voltage application scenarios, in order to achieve high power output and ensure the power quality of medium and high voltage load, it is necessary for DVR device to adopt multi-level series connection, and two groups of NPC three level series connection can ensure the voltage compensation within 10kV. Fig. 1 (d) shows hybrid multi-level open end winning of the independent DC bus. When the voltage level requirement is not high, the topology of two groups of series inverters can be flexibly changed, which can also achieve multi-level output. At the same time, when one end of the inverter stops working due to fault, it can still ensure the other end of the inverter works normally, and improve the reliability of DVR device.

Control strategy of open-end winding DVR
Taking the structure of two-level open winding DVR of common DC bus shown in Fig. 1 (a) as an example, the main circuit is composed of two groups of two-level converters in series. In order to reduce the hardware cost, two groups of converters share the same group of DC bus, which is then transmitted to the grid and load through LC filter and isolation transformer. Due to the common DC bus structure, the three-phase DVR can be controlled separately for each phase. The single-phase static ABC coordinate system is established as follows: Where U1 and U2 are the voltage at both ends of the transformer. Udvr is the voltage value injected to compensate the load voltage, and the load is composed of Ll and rl. The DVR filter is Lf, rf and Cf, and the leakage impedance of the transformer is Lt and rt. The transformer transformation ratio is 1: n. If, Ic and Il are respectively filter inductance current, capacitance current and load current. The output voltage of the converter is Ui, which is composed of the voltage Ux1 and Ux2(x=A,B,C)of inverter 1 and inverter 2.
According to formula (1), the mathematical model of the system in three-phase static coordinate system can be expressed as follows: is the switch function of the inverter phase arm. The upper arm on is 1 and the lower arm on is 0.
Convert (6) to synchronous rotation coordinate system as follows: Therefore, the equivalent circuit in two-phase coordinate system is shown in Fig. 2.
(b) q axis equivalent circuit Based on the DVR topology shown in Fig. 1 (a), the control principle of the device is analyzed. The control of DVR mainly includes two parts, namely, obtaining the voltage reference value compensated by DVR itself and outputting the corresponding compensation voltage according to the reference value. The compensation performance of DVR is closely related to the control strategy it adopts. At present, the most important linear control is divided into feedforward control and feedback control. Feedforward control is prone to compensation error in practice, and voltage feedback control is often used for precise control demand, as shown in Fig. 3. kv, kc and ki are the control parameters of outer loop, middle loop and inner loop respectively. In the inner loop design, inductor current feedforward is introduced, and inductor current is introduced into the compensation voltage loop through band-pass filter. The expression of band-pass filter is as shown in formula (8), and its conduction frequency is the resonance frequency of LCL filter. Its purpose is to introduce resonance component in the control link to realize the resonance suppression of LCL filter and ensure the load voltage compensation effect.

Common mode voltage suppression modulation strategy
For the DVR structure with open-end winding, the DC side can choose either the independent DC bus structure or the common DC bus structure. Because the independent DC bus structure needs to provide two groups of DC sources, which increases the hardware cost, the common DC bus structure is often used in practical application. However, the common DC bus structure has its own problems [5]. First, its DC voltage utilization ratio is slightly lower than that of the independent DC bus structure, and second, the common mode DC bus contains zero sequence path. Because of the existence of zero sequence path between two groups of inverters, three times of zero sequence current will appear in the filter inductance current, and the filter capacitance has very poor ability to suppress the three times of current, so it will appear in the transformer. The zero sequence current component makes the transformer appear bias phenomenon, which affects the quality of DVR compensation voltage. The source of zero sequence current is that the output voltage of two groups of inverters contains common mode component. To suppress the zero sequence current is to eliminate the common mode voltage of the inverter.
As can be seen from Fig. 1 (a), the common mode voltage of each inverters is: Considering the switch function, the common mode voltage of DVR system is as follows: The common mode voltage of the converter can be eliminated by ensuring that formula (10) is zero at any time.   Fig. 4 shows the space vector of two-level structure inverter 1 and inverter 2. Different space positions 1~6 and 1'~6' are generated by their respective switch functions, and then they are arranged and combined according to the space angle to get the series space vector diagram of two-level structure inverter, as shown in Fig. 5 (a). It contains 19 voltage space vectors, among which seven voltage vectors do not produce common mode voltage difference to the system, as shown in Table 1. The space positions of seven voltage vectors are H, J, L, N, Q, S, O, and the spatial distribution is shown in Fig. 5 (b). After superposition of seven voltage vectors, the common mode voltage difference of the system is zero, so there is no common mode current caused by common mode voltage difference in the grid connected current, which affects the power quality.   shows the composite space vector without common mode voltage difference. There are two construction modes for each composite vector (except zero vector). When DVR considers the specific pulse occurrence of each inverter, it is necessary to make two adjacent vectors of each inverter act in the unit switch cycle, so as to ensure that each switch is only turned on and off once in the switch cycle. Taking sector 1 as an example, in Fig. 5 (b), the composite vector us is composed of two groups of vectors: OS and OH. According to the triangle sine theorem, the vector lengths of OS and OH are respectively: sin(30 ) / sin120 Where θ is the operation angle of the composite vector. Considering the pulse generation rule, the OS vector is composed of 13', and the oh vector is composed of 24'. Because  Assign the composite vector Us1 and Us2 to the respective vectors of each inverter, as shown in Fig. 4, Us1 is composed of two groups of vectors 1 and 2, and θ1 is the operation angle of Us1. Us2 is composed of two groups of vectors 3' and 4', and θ2 is the angle between Us2 reverse direction and α axis. At this time, the acting length of vectors 1 and 3' is: The comparison formula (12) and (13) can be concluded as follows: It can be seen that inverter 1 and inverter 2 only need to generate their own vectors according to formula (14) to realize the common mode voltage difference suppression without changing the traditional two-level SVPWM pulse generation, which simplifies the program design.
The maximum value of the composite vector phase voltage peak value is 2 3 Udc/3 in Fig. 5 (a). After the common mode voltage difference suppression, the DC voltage utilization rate slightly decreases, and the maximum value of the phase voltage peak value is Udc, as shown in Fig. 5 (b). However, compared with the maximum phase voltage peak Udc/ 3 of traditional NPC topology, the voltage utilization ratio is still increased by 24.4%.

Experiment
In order to verify the above theoretical analysis, an openend winding three-phase DVR experimental platform is built. The topological structure is shown in Fig. 1 (a), the main circuit parameters are shown in Table 2, and the software is realized by DSP28335 control chip.  Fig. 6 is the experimental waveform of grid voltage drop. CH1 is A-phase filtering inductor current, and CH2 is A-phase load current. CH3 is A-phase grid voltage, and CH4 is A-phase load voltage. Adjust the grid voltage to make it drop to 300V, and set the load voltage to 400V. At this time, the load voltage follows the command to maintain the load voltage unchanged. Through the common mode voltage suppression strategy, the zero sequence voltage of the filter inductor current is guaranteed. At the same time, the validity of DVR three loop control strategy is verified.

Conclusion
In this paper, the main circuit topologies of DVR with various open-end winding series structures are proposed to further improve the diversity of DVR applications. According to the mathematical model of open-end winding DVR, it is clear that the composite vector is composed of two groups of inverters. The three loop control strategy of load voltage outer loop, inductance current middle loop and compensation voltage inner loop is proposed to effectively suppress the compensation resonance voltage caused by LCL filter. According to the open-end winding structure, the common mode voltage suppression modulation strategy is analyzed, which can completely suppress the common mode voltage of the system. At the same time, the correctness of the three loop control strategy and common mode voltage suppression modulation strategy of the open-end winding topology is verified by experiments.