Performance evaluation of SRAM design using different field effect transistors

. SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.


Introduction
Mostly SRAM cells are built with MOSFET, but as the channel length of the MOSFET enters into the nano-meter range the short channel effects will threatens the performance of the SRAM. To Overcome these short channel effects, we can opt the different type of field effect transistors in place of the MOSFET, CNTFET and FINFET.CNTFET(Carbon Nano Tube Field Effect Transistor) is a type of transistor that uses the carbon nanotubes as channel material instead of semiconductor material like silicon [1][2][3]. In CNTFET, the CNT(Carbon Nano Tube) serves as the semiconductor channel between the source and the drain terminals similar conventional MOSFETs as shown in Fig 1. These Carbon Nano Tubes are made of carbon atoms that are arranged in two-dimensional honey-comb lattices. CNTFETs have potential to revolutionize the field of electronics and enable the development of new technologies that are not possible with traditional silicon based devices [4][5][6][7]. A FinFET (Fin Field-Effect Transistor) is a type of 3D transistor that is widely used in modern electronic devices and many other digital systems. In planar FET the Gate is placed above the channel and there is leakage current flowing from the source to drain when the gate is off. But in FinFET the channel is thin vertical fin and gate is wrapped around it as in Fig 2. This help in better controlling of the channel and thus reducing the leakage current and improving the electrical properties. FinFETs, however, are highly scalable, meaning that they can be manufactured at increasingly smaller process nodes, allowing for higher transistor density and improved performance [8][9][10][11][12]. GNRFET (Graphene Nanoribbon Field-Effect Transistor) is a type of transistor that uses graphene nanoribbon as the channel [13][14][15]. Graphene nanoribbons are narrow strips of graphene, a single layer of carbon atoms arranged in a hexagonal lattice structure. GNRFETs have several advantages over other types of transistors and that consume low power and have high performance compared to MOSFET. This makes GNRFET a promising technology for future electronic devices due to their unique properties and high performance applications [16][17][18][19][20][21][22][23].

SRAM design and operation
SRAM (Static Random Access Memory) is a type of memory cell used in many digital applications. It is called "static" because it does not require periodic refresh cycles to maintain its contents, unlike Dynamic RAM (Random Access Memory), which requires a constant refresh.
The 6T SRAM cell consists of six transistors in which four transistors are arranged in a cross-coupled latch configuration. The two cross-coupled inverters store the binary value of 0 or 1, and the two access transistors provide read and write access to the cell. These access transistors are controlled by a word line, which is used to select the cell for read or write operations.

Write Operation:
Let assume that memory cell has to hold bit one which means Q=1 and QB=0.Apply high voltage to write line i.e., (WL=1).Then Supply high voltage (1v) to BL and low voltage (0v) to BLB. The voltages that we applied through BL and BLB will get to Q and QB then the data bit will continuously latch between two cross coupled inverters. And make write like as low then hold of bit takes place.

Read Operation:
Let assume that memory is already holding bit one i.e., (Q=1 and QB=0).In order to perform read operation we should make word line as high (WL=1).Now voltage from the Q will flow into BL and QB will flow into BLB.BL and BLB terminals are connected to sense amplifier which gives amplified differential voltage between BL and BLB. By observing the output voltage from the sense amplifier, we can identify the data that is stored in SRAM cell.

Hold Operation:
To perform the hold operation we should make the word line as low (WL = 0). Then the data bit we stored in the SRAM cell will continuously latch up in the cross coupled inverters.  By observing the Table 1 we can conclude that CNTFET has the lower read and write delays compared with different field effect transistors. The power dissipation of different Field Effect Transistor during the read and write operation is interpreted in Table 1. Other than the MOSFET different FETs have the lower power dissipation. Power Delay Product (PDP) is a metric used to measure the efficiency of digital circuit. It is defined as the product of the power consumed by the circuit and delay of the circuit. Table 1 consists the read and write PDPs of the different field effect transistors.      Among the different FETs, CNTFET has less read and write delays, power dissipation and has the marginal SNM. We can also improve the performance of the SRAM by adjusting the different parameters of CNTFET i.e.. diameter of the CNT (Dcnt), Number of the CNT tubes (Ncnt) and flat band voltage(Vfb).As the diameter of the CNT (Dcnt) increases the read and write delays of the SRAM will decreases. This is because larger diameter of CNTs has the lower resistance and capacitance, which allows the transistor to have faster switching speed. Read and Write Delays of the CNTFET SRAM by varying the diameter of the CNTs are interpreted in Table 3.   Table 4 shows the read and write delays of SRAM with variable flat band voltage. In a CNTFET, the number of CNT tubes used in the device can also have significant impact on its electrical properties and performance. Table 5 is composed of the varying CNT tubes with decrease in read and write delays of SRAM. Analysing the figure 14 that we can conclude that 1V VDD has less read and write delays compared to the other voltage ranges.

Conclusions
SRAM is the most used memory in many applications and it perform better way and have more stability than DRAM. In this work, we have analysed the performance of the 6T SRAM cell which is built by using the different field effect transistors. We have used the different field effect transistors such as FinFET, GNRFET and CNTFET to design a SRAM. All the SRAM design have compared with the conventional MOSFET designs. The comparison of simulation results have done at 32nm technology node which shows the delays, power dissipation, power delay product and static noise margin(SNM) is more marginal for CNTFET compared to other different FETs. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively.