Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders

: This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 32nm technology node and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. The effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. Dependence of threshold voltage on the geometry of carbon nanotube and graphene nanoribbon makes it feasible to be used for ternary logic design. It is analyzed that CNTFET based circuits are energy efficient than the GNRFET-based circuits. It is also concluded that the CNTFET-based circuitshas less power-delay product (PDP) when compared to GNRFET-based circuits. CNTFET-based THA is 23.5% more efficient than GNRFET-based THA and CNTFET-based Tmul is97.8% more efficient than GNRFET-based Tmul.All the digital circuits have been simulated using HSPICE tool.


Introduction
CMOS is one of the most used semiconductor device in low-power VLSI design. However, we can observe short channel effects that increases the leakage currents and power dissipation complications in small chips. Due to this many scientists proposed various alternative solutions in the transistor technologies like FinFET (Fin Field-Effect Transistor), Spin-wave, Single-electron devices, CNTFET,GNRFET. Among all different transistor technologies, CNTFET and GNRFET has a higher performance. The CNTFET and GNRFET model includes the various parameters such as the allocation of carbon transmit speed and better mobility, then, it can be appropriate to various alternative circuits [1][2][3][4][5][6]. It can also used in integrated circuits and it can cause low voltage, which results in lower power consumption. The CNTFET structure uses CNT as a channel in between source and drain terminals similar to conventional CMOS structure which is shown in Figure 1 [7][8][9][10][11][12]. The GNRFET structure uses GNR as a channel in between source and drain terminals similar to conventional CMOS structure which is shown in Figure  4.The binary circuits require high energy consumption. Whereas, MVL circuits reduce the consumption of energy because the MVL digit can hold over two states of data. The ternary unary operators, CNTFET transistor, transmission gates and applies dualvoltages (Vdd, Vdd/2) in the designs to decrease the PDP of the proposed TFA(Ternary Full Adder). This technique is used to save battery consumption.

Fig 2. Structure of GNRFET
The structure of GNRFET looks like similar to the traditional MOSFET which is shown in Figure 4. The GNRFET consists of four terminals with gate, drain, source and bulk terminals. In which undoped GNRs are placed under the gate terminal while heavily doped placed under source and drain terminals [14][15][16][17][18][19][20]. The device on and off conditions are based on the potential available at the gate terminal. The V-I characteristics of GNRFET are also same as conventional MOSFET.
The width (W) of GNR is calculated as Where, 'N' represents no of dimer lines which is proportional to width of GNR, a is the lattice constant i.e., 0.142 nm. The dimer lines are inversely proportional to band gap of GNR. The voltage that is required to turn ON the FET is called as threshold voltage. The threshold voltage of GNRFET is inversely proportional to the width of GNR and is given as below Where, = 2| | is the band gap and e is the unit electron charge. α=0.27 for N=3P; α=0.4 for N=3P+1; α=0.066 for N=3P+2, △ = ℎ , ħ = 6.5821 × 10⁻ , =10 6 .
For the dimer lines 6 the width of GNR is 0.86 nm and the threshold voltage is 0.43 V from (2). The width of GNR is calculated by dimer lines N using (1). The dimer lines of GNR increases as the width increases and the dimer lines is inversely proportional to band gap. GNRFETs provide equal opportunity to control threshold voltage by altering the width of GNR. We use multi width GNRFET design for ternary logic implementation [21][22][23][24]. The Stanford GNRFET SPICE model is used for simulating the GNRFET based ternary logic gates. This is a SPICE model developed for unipolar, MOSFET-like GNRFET devices and it depends on the presumption of ballistic transport, which is just precise in a short channel GNRFET. In addition, it represents accurate and companionable GNRFET configurations for HSPICE simulations [14][15][16]. This paper presents the brief introduction to CNTFET and GNRFET in section 1.Ternary gates are discussed in Section 2. Proposed GNRFET -based THA and Tmul circuits in Section 3.Finally section 4 concluded this work.

Proposed designs and simulations:
In this work, the circuits are designed by using CNTFETs .In CNTFETs the threshold voltage depends on the carbon nano-tube (CNT) diameter by the following equation, Where Dcnt is the CNT diameter.
This proposed circuits have 2 diameter CNTs, where D1=1.487 nm and D2=0.783nm.The operation of the CNTFET and GNRFET Transistor, and the relation between the threshold voltage and the CNT diameter and Dimer Lines is in Table 9.

Ternary Half Adder
A ternary half adder is a digital Circuit that performs addition of two ternary (base-3) digits, resulting in a sum digit and carry digit. The truth table is as shown in Table 10.  Themathematical expression of sum and carry for ternary half adder can be obtained from Table 2 are given below. The above truth table can be also represent as shown in Table 11. The Ternary Half Adder circuit as shown in Figure 2. For CNTFET based Ternary Half Adder, the transistors diameters and their corresponding threshold voltages are in Table 4.  T4,T11,T14,T19,T22,T24,T26,T28  ,T30,T32T34,T35 0.783 0.559 Figure 3 shows the proposed THA with 35 CNTFETs using unary operators, transmission gates (TGs), and dual-voltages (Vdd, Vdd/2). Without using cascading TGs, which is the advantage compared to THA with 34 CNTFETs in that used cascading TGs. Because cascading TGs provide higher propagation delays and energy consumption. When the voltage supply (Vdd) decreases in a transistor then the propagation delay will increase. Therefore, any path from inputs to outputs contains transistors that have voltage supply equal to Vdd/2, that path will have higher propagation than other paths that have voltage supply equal Vdd. The Propagation delay of Ternary Half Adder is in Table 4.

Ternary Multiplier
The multiplier circuit has two input variables and two output variables. The input variables are the cumulative number and the output variables are product and carry. Table 7 shows the Truth table of Ternary multiplier.  The mathematical expression of product and carry for ternary multiplier can be obtained from Table  14 are given below. Product = 2 .(A1B2 + A2B1) + 1 .(A1B1 + A2B2) Carry = 1 . (A2B2) The above truth table can be also represent as shown in Table 8 and Table 9.   Table 10.

Voltage Variations
This paper analyses and simulates the proposed and all the investigated THAs and TMULs for Voltage variations. The proposed circuits and all the investigated circuits simulated with voltage variations (from 0.8V to 1V).The results are as shown in Figure 16.

Conclusion
This work presented a Nano transistor based digital circuits to improve the performance of the digital circuits and proposed novel designs of 32 nm GNRFET-Based Ternary Half Adder and Ternary Multiplier using proposed Unary Operators combined with transmission gates with out using ternary decoders, basic logic gates, or ternary encoders. And the comparison of the effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. In CNTFET threshold voltage can be controlled by diameter which depends on the chirality vector. In GNRFET threshold voltage can be controlled by width which depends on number of dimer lines. The design process utilizes different techniques in terms of transistor arrangement, two power supplies (Vdd, Vdd/2), transistor count reduction to reach the final target. The Ternary Half Adder and Ternary Multiplier are designed using industry standard HSPICE to achieve propagation delay and power. Finally, the proposed THA and TMUL can be implemented in low-power nano-scale embedded systems and IoT devices to save battery consumption.