Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

: Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.


Introduction:
Multiple Valued Logic (MVL) and its' applications have been studied extensively over the last couple of decades due to the ability of the MVL logic devices to provide an exponentially higher information density compared to the binary logic. In Binary or Boolean logic system (base 2), each logic bit can have two possible values: low (0) and high (1). Whereas, in the MVL system (base 3 or more), each digit can have three or more possible values leading to significantly higher information density with smaller logic gates and reduced circuit complexity. As a result, the energy consumption, area, and circuit overheads and other costs for each bit of information would decrease in the MVL system [1]. For example, in the ternary logic system, it takes only log32n bits to represent an n-bit binary number [2], which reduces the computational complexity to a large extent and thus enhances the power and area efficiency of the system. Multiple valued logic can be ternary (radix 3), quaternary (radix 4), quinary (radix 5), etc. However, ternary and quaternary logic systems have drawn much attention from the research community. The ternary logic system appears to be the most feasible MVL system that can be adopted in the near future because of its simplicity and ease in distinguishing different logic levels as in the binary system. At smaller technology nodes, the supply voltage is limited to a value equal to or less than 1.2 V. Therefore, a higher number of discrete voltage levels needed to identify different logic values within this limited supply range (0 to 1.2 V) would be challenging and susceptible to noise and other signal integrity issues. As a consequence, most of the recent research workfocuses on ternary logic and memory. The initial efforts toimplement ternary logic are based on the prevailing CMOS and other technologies available since 1974 [3][4][5]. Dueto short channel effects, scaling limitations, DIBL, energyconsumption, and other signal integrity issues, conventionaltechnologies are not appealing for the MVL system. Newmaterials and new device technologies like carbon-basedFETs, QDGFET, and Memristor [6][7][8] are being explored to overcome these limitations and implement reliable MVL circuits.
Carbon-based Field Effect Transistors (FETs) are drawing widespread attention due to their outstanding electrical properties and integration capabilities. Carbon-Nano-Tube-Field-Effect-Transistor (CNTFET) and Graphene-Nano-Ribbon-Field-Effect-Transistor (GNRFET) are the two forms of carbon-based transistor that have become trendy research topics. Different pieces of literature are found which work in CNTFET and GNRFET based ternary logic design [9][10][11][12][13][14][15][16][17][18][19][20][21] which uses the threshold voltage control method for implementing different ternary logic circuits and arithmetic circuits. Generally binary adders add 3 inputs to give sum and carry. But in ternary logics we can add 4 inputs at a time to produce final sum and carry which will reduce the number of stages in the Wallace tree multiplier.In this paper, we present a design approach for CNTFET based ternary logic circuits because of low supply voltage and multi threshold voltage

Ternary adders and simulation outputs:
The sum output is generated using a ternary XOR gate. When both inputs are 0 or both inputs are 2, the output of the XOR gate is 0. When one input is 0 and the other input is 1, or oneinput is 1 and the other input is 2, the output of the XOR gate is 1. When one input is 0 and the other input is 2, or both inputs are 1, the output of the XOR gate is 2.The carry output is generated using a ternary AND gate. When both inputs are 0 or one input is 0 and the other input is 1, the output of the AND gate is 0. When one input is 2 and the other input is 1 or both inputs are 2, the output of the AND gate is 2. When both inputs are 1, the output of the AND gate is 1.If the sum output of the ternary half-adder is 2, then a carry has been generated and it needs to be propagated to the next higher-order digit.     In the above table, the input digits A, B, and C represent the digits being added, and produce the sum and carry respectively. For each input combination of A, B, and C, the ternary fulladder performs the following steps:Add A and B to produce a temporary sum T.Add T and C to produce the final sum S.Determine the carry by checking if the sum S is greater than or equal to 3.If S is 3 or more, then there is a carry is 1.In general, when all three inputs of a ternary full-adder are the same, the carry out will be equal to 1 if the input is 2 or greater, and equal to 0 if the input is 0 or 1. The sum output will be 0 in all cases.    We designed Half adder , 3 input Full adder and 4 input Full adder using SUM , CONS and ANY gates. The total transistor count of the ternary 3 input ternary full adder is 124 , and total transistor count of the 4 input ternary full adder is 194.In the 4 input ternary adder. In the first design(TA) , first two inputs are added and then the sum of first two inputs is added to third input . The total resultant is then added to the fourth input to give the final sum.In this design , even all the inputs are available in the begining stage , we are adding only one input in each stage similar to the conventional method.This will result in more delay .To overcome the above we proposed the second design. In the second design(TC), the four inputs are added with two SUM logic seperatly in the first stage itself and the generated two sums are added with another SUM logic.By this method the is reduced.The advantage of ternary adders over the binary adders is we can process 4 inputs at a time instead of 3 inputs so that the delay can be decreased.
This proposed 4-input adder will be used in many ternary multiplier applications. The partial products generated in the multipliers are added by proposed ternary adders to generate the accumulate. The generated accumulates are furthur added with fast ternary adders to generate final result.
We have also designed 4*4 bit multiplier using proposed adder. First the partial products are obtained using the 1-bit multiplier. The generated partial products are grouped and added with 2-input,3-input, 4-input proposed Ternary adders to generate accumulate. The accumulate is then added with Fast ternary adder to give final result. In the normal conventional method we use to add only two/three inputs to generate the accumulate. In the proposed system can add upto 4-inputs at a time.This will reduce the no.of stages in the multiplication process.As the no.of stages are reduced , the delay is also reduced.