Implementation of three stage comparator using a modified latch with sustainable resources

. In this paper, the current study uses a lector technique to modify the latch. The Lector approach is one of the top low-power methods for IC technologies. The locking mechanism is the third stage in our proposed design for a three-stage comparator. The lector approach is used for the three-stage comparator circuit in this case and its modified version. Pre-amplifier stages are the first two levels. The improved performance of this comparator circuit uses two sets of complementary biased two-stage preamplifiers. The traditional three-stage amplifier decreased the latency, while the modified version of the modified three-stage amplifier focused on the kickback noise. The proposed design of this three-stage comparator, which employs a lector approach, concentrates mainly on lower consumption. Tanner EDA was used to build and simulate this complete schematic. Materials having a lesser environmental effect are chosen, such as those that use fewer resources or are simpler to recycle after a product's lifespan and sustainability.


Introduction
A comparator is an essential part of analog to digital converters.These applications place a greater emphasis on high performance, high resolution, and kickback noise.In these circumstances.Conventionally, there are manydifferent configurations of comparator structures, such as the two-stage op-amp, TIQ comparator, and Miyahara's comparator.Various comparator combinations alose CMOS technology, GDI logic, and other technologies.Many different techniques are created to deal with the difficulties of the lowvoltage design, including supply boosting techniques [1,2], strategies using body-driven transistors [3,4], current-mode design techniques [5], and techniques using dual-oxide processes.Greater supply voltages can be handled by these techniques.The "boost" and "bootstrapping" procedures entail raising supply, reference, and also clock voltage to clarify the input range and switching problems.Although all these techniques are more effective, especially about "UDSM CMOS technologies."Body-driven MOSFETs now operate as depletion-type devices since Blalock's [3] body-driven methoddoes not require a threshold voltage.It is advisable to design specific circuit topologies for low-voltage operations that prohibit stacking an excessive number of transistors between the supply rails, even if doing so does not make the circuit more complicated.There have also been developments in technology.New circuitry was added to the design of the original comparator, which helps to speed up the active comparator at low-level supply voltages [6][7][8][9].Four different three-stage comparator circuit topologies have been compared in this paper.Circuits with and without lector methods, three-stage comparator circuits, and altered variations of these circuits are also included in the comparison [10][11][12][13][14][15].
The monolithic linear component known as comparators may be the most underappreciated and underused.Comparators are among the most versatile and widely used components thus, it is terrible.The IC op amp, whose adaptability allows it to rule the analog design world, is primarily to blame for the lack of attention.

Earlier work
Low-power, high-speed ADCs are required for baseband processing in digital wireless communication applications like Ultra Wide Band (UWB) and Wireless Personal Area Networks (WPAN) to convert Radio Frequency/Intermediate Frequency signals into digital form.The comparator is a crucial component that is frequently used in ADC.ADCs, data transmission, and switching power regulators, among many more uses, all employ comparators.When it comes to high-speed ADCs, the comparator design is crucial.Key design considerations for comparators include power consumption and speed.Regardless of the architecture, the comparator is a crucial component for all high-speed ADCs and plays a significant role in the overall performance of data converters.The maximum sampling rate, bit resolution, and overall power consumption are all included.The study of conventional comparator circuit topologies and operations is more thoroughly covered in this part.The two-stage, three-stage, and modified versions of the Miyahara comparator are discussed in this section.The Miyahara two-stage comparator's (see Fig. 1) regeneration pace was originally constrained by a small current source, however, that source is no longer there.This is because the gate-to-source voltage of the latch, which is VDD/2, is twice as high as the gate-source voltage of the latch's input pair, M6-M7, which is VDD.A decrease in the transistor's quantitythat is stacked.As an outcome, the power supply's needed voltage is satisfied.
In Fig. 1 latch input pair M6-7 clearly shows how the poorpMOS hole mobility limits regeneration speed.In comparison to the nMOS electrons, this mobility is two to three times lower.To significantly speed up regeneration, we plan to utilizenMOS transistors in place of the latch input pair.The three phases of action are reset amplification and regeneration.The comparator is reset when the CLK isequal to 0. During the period of amplification when the CLK = 1, the input signal which is VIP-VIN is amplified and sent to the latch stage.During the regeneration phase, the outputs of OUTP and OUTN regenerate to VDD or GND.As it was mentioned before, the latch stage's usage of a pMOS input pair imposes limitations on the design of this architecture.By employing, nMOS input pairs for the both latch-stage and first-stage preamplifier and adding an extra preamplifier stage, regeneration can be sped up.Furthermore, the operation of input pairs at the saturation region level at the outset of comparison assures minimal input noise (referred).The extra-preamplifier stage will provide voltage gain, acceleration, and regeneration while lowering input noise and referred offset.The additional stage itself increases the time it takes for the amplified signal to reach the latch stage because it now passes through two stages rather than one, even though the secondary preamplifier helps to speed up the process.It is necessary to evaluate if the advantage of this additional delay warrants it.As seen in the above Fig. 2, the outputs FP, and FN decrease to the GND after completion of the first step stage of amplification.The second-stage input pair M8-M9 features result from a large gate-source voltage, which is comparable to VDD.RP and RN may be immediately pulled up because the current on M8-M9 isstrong.This indicates that the second stage's additional delay is rather little in comparison to the latch stage's significant delay.This makes to know that the second stage is a dynamic inverter, which doesn't add more delay.To reduce kickback noise [9] and speed up the process even more, An advanced model of the three-stage comparator, shown in Fig. 3, isprovided in this short.The three-stage comparator can be distinguished from its modified counter part by the added initial two amplifier stages and additional pair of pMOS inputs for the pre-amplifiers (first two stages).M11-12 works to reduce the kickback noise of nMOS input pair M1-2.Also accelerating, regeneration while reducing the kickback noise and input referred offset is the additional signal applied via additional routes M29-32 to the latching nodes of OUTP and OUTN.The followingdescribes how these extra circuits operate.CLK and CLKB are both set to zeroduring reset.The RP1 and RN1 are set to GND in contrast to the FP1 and FN1, which reset to VDD.Turning off M30 and M32 in this way prevents static current from flowing via the additional path which is M29-32.Throughout the amplification stage phase, CLKB decreases to 0 and CLK increases to 1. R stands for a rise, while RN1 and RP1 climb to VDD.Then, the FP1 and FN1 turninto GND.(F represents fall.The extra routes are momentarily activated because of RP1 and RN1 rise before FP1 and FN1 fall, drawing differential current from latching nodes OUTP, and OUTN.Input noise and offset are reduced by the resultant differential voltage at the comparator's input, and their generation phase at the output points (OUTP and OUTN) is accelerated.The remaining channels are again switched off to stop the static current once FP1 and FN1 get close to GND.

Proposed work
In this section, the significance of low-power techniques isexaminedalongwith a detailed analysis of the lector approach.Low-power VLSI circuit design requires careful consideration of leakage current.Low power consumption components and design offer additional benefits.Cost, area, and performance were historically the three primary design considerations for VLSI.But when technology becomes both more complex and less intelligent, low power is now as significant as these other characteristics.Leakage current results from scaling down, which presents a significant difficulty for VLSI design.

Lector approach
Our strategy for cutting leakage power is based on the fundamental notion that transistors in the circuit that connects supply voltage to the ground should be properly stacked.When more than one transistor is turned off, the voltage supplied via the grounded route is significantly less dripping than when a single transistor is turned off.One of the two leakage control transistors (LCTs) in our design, which has two CMOS gates, is located near the cutoff zone.Here, the latch, the third stage of the three-stage comparator, is altered using a lector approach.Usually, there are two inverters connected back-to-back in a latch configuration.The latch utilized in the construction of this inverter is based on the lector shown in Fig. 4. The modified complete schematic for the three-step comparator is shown in the following illustrations Fig. 5 and Fig. 6.A three-stage comparator of a first two-stage preamplifier and latched comparator using the lector technique is shown in below Fig. 5.In the lector technique LCT scalled leakage controlled transistors are used and also it is used to eliminate the Leakage current which reduces the power consumption.So that, it gives a better result.and latched comparator using LCTs as shown in Figure 6.It will reduce the power consumption and leakage current."Our strategy for reducing leakage power is based on the effective stacking of transistors along the path stage from the supply voltage to transistor turn OFF stage in a path from the supply voltage to ground is far less leaky than a state with only one transistor OFF stage in any supply to ground path".In our technology, Each CMOS gate receives two leakage control transistors (LCTs), one of which is placed close to the LCTs cutoffregion of operation.The pre-amplifier is a preamp, and also a kind of amplifier.is a device that increases the signalstrength before giving it to the main amplifier.

Experimental results
Tanner EDA Software is used to analyze the 45nm CMOS chipset.This software uses S-Edit to construct the schematic, Tspice to produce the automated netlist, and output parameters are presented to simulate the design.Use W-edit to view the simulation waveforms.The suggested block diagram schematic employs the Lector method.

Conclusion
The three-stage comparator and its modified variant, both of which benefit from being quick and quiet, are described.In the suggested work, a latch-based comparator is replaced with a lector method to reduce power usage.These comparators work well when SAR ADCs need to run quickly and with excellent resolution.Quantitative outcomes also support the viability of these comparators.The three-stage comparator's implementation was influenced by the maximisation of long-term viability and the minimisation of environmental effect through the use of sustainable resources.

2. 1 AFig. 3 .
modified version of a "three-stage comparator".(a) nMOS input pair in the pre-amplifiers (original first two stages).(b) An additional pair of pMOS inputs for the pre-amplifiers (first two stages).(c) The latch stage (third stage).

Fig. 5 .
Fig. 5. (a) Pre amplifier (First two stages), (b) Latch stage (Third stage) A comparable update and redesign using the Lector technique has been made to the conventional three-step comparator.As shown in the subsequent Fig. 6, the pertinent circuit diagram: A three-stage comparator of nMOS input pair and pMOS input pair pre-amplifiers

Fig. 7 .
Fig. 7.The suggested circuit's schematic of the modified three-stage comparator.

1 .
It shows that the suggested circuit is superior in terms of power and latency.

Table . 1
. Comparing proposed and modified procedures.