Efficient Nano-Scale Design of TIEO Based Reversible Logic Toffoli Gate Priority Encoder in Quantum-Dot Cellular Automata

. The goal of this research is to create a QCA-based reversible priority encoder. It is one of the most crucial parts of the encoding and decoding process. This novel nanotechnology, known as quantum-dot cellular automata (QCA), shows promise as a foundation for the development of reversible circuits. This paper proposes a simple, reversible, 4-2 line priority encoder design for the QCA platform. Using the simple and cheap Toffoli gate architecture, a reversible encoder circuit may be built. To analyze the proposed designs' structural soundness, the simulation program QCA Designer is used.


Introduction
Due to their tiny element size and significant power consumption, devices based on complementary metal oxide semiconductor (CMOS) technology are limited in their performance.It's true that many researchers are considering how to build complex logic circuits at the nanoscale using low-power methods.It is necessary to think about a CMOS replacement in order to get the reduced design density and high-speed switching.A quantum-dot cellular automaton (QCA) is presented as a novel transistor-free paradigm for the creation of a nanoscale device with high density and terahertz speed switching.There are many references [1-3] that go into depth on the experimental features and physical implementations (metal-island, semiconductor, magnetic, and molecular QCA).The first functional quantum cell based on a primitive material has just been constructed [4].An issue with CMOS technology is its tendency to dissipate a lot of electricity.Energy loss during computations may be prevented with the help of the reversible computation, which has been given [5].The studies confirm this.In reversible logic, the reversible gate plays a key role.Several types of reversible gates have been proposed by the research community [5].The Toffoli gate is widely used [6][7][8][9] because of the variety of tasks it can do.Nanotechnology, quantum computing, and optical computing are all areas where reversible logic circuits are receiving a lot of attention.The use of erasable logic circuits in quantum computers is novel.Traditional methods of combining logic cannot be easily applied to reversible circuit models.A reversible logic circuit cannot function without producing garbage results.In most cases, discarded gate products are considered waste.The quantum cost of each reversible logic gate must be paid.This paper details the QCA design of the most common reversible logic gates in use today.In this article, we demonstrate a simple method for building a reversible 4-to-2 QCA priority encoder using a Toffoli gate.This design method may be used to create an n-bit version of the Encoder.Methods of analysis, equivalence, and simulation are also explored.

Related Works
QCA is increasingly being used in the literature to create reversible circuits.Creating a fast and efficient XOR gate is one of the most pressing issues in this field of study because of the widespread use of the Exclusive-or (XOR) element.The use of three regular majorityvoting gates and inverters is standard in many modern designs.In [10], an alternative technique for designing XOR gates using a 5-input majority gate is shown, which has many advantages over the standard approach.However, a compact design of the XOR gate using the cell interaction technique [11,12] has recently been described, and this has considerable benefits when it comes to achieving sophisticated circuit design with low complexity.
Numerous investigations [11,12] have shown that reversible logic is a practical paradigm for quantum computing.The primary benefit of reversible logic circuits is that they preserve data in both directions.Numerous publications detail the many possible layouts for reversible logic gates.In optical computing and quantum cellular automata, reversible logic circuits are crucial, and these reversible gates make this possible.The sequential circuit layout and the reversible circuit layout, both having addition, multiplication, and division applications in combinational circuits, have been studied [13][14][15][20][21][22].Low power designs, quantum computing, and the communication industry are just a few of the many applications for reversible logic gates.The nano communication techniques described in [16][17][18] show great interest in using these reversible logic gates.Both the structure of the reversible gate and the QCA design and the simulation results for both designs are presented in the paper.
There are several QCA implementations of the Toffoli gate.The Toffoli gate concept was implemented in [19] using four large-area majority gates.The architecture makes use of four MGs, one of which performs the role of an OR gate in addition to the three AND gates.Recently, a novel QCA implementation [23,24] of a Toffoli gate-based reversible priority encoder has been developed.There are a total of five MGs in this layout, four of which function as AND gates and one of which performs the role of an OR gate.There is a 1.5-cycle delay introduced by using 64 quantum cells in the design.This paper has seven different embellishments.Parts 1 and 2 provide an overview of QCA and the literature that surrounds it.The process by which QCA technology operates is outlined in Section 3. The reversible logic, suggested design, and implementation of a Toffoli gate are discussed in Sections 4 and 5, respectively.The simulation results were analyzed in section 6 by contrasting the various features of the proposed architectures.Section 7 provides a brief recap of the proposed circuits and wraps up with thoughts on where to go from here.
The Toffoli gate has numerous QCA implementations.Work [19] used four majority gates with a sizable area to accomplish the Toffoli gate design.The design employs four MGs, with the fourth acting as an OR gate and the other three as AND gates.Recently, a Toffoli gate-based reversible priority encoder was given a unique QCA implementation [23][24].In this design, there are five MGs total, four of which are employed as AND gates and the final MG as an OR gate.The 64 quantum cell implementation of the layout causes a 1.5 clock cycle delay.
Seven different decorative elements make up this paper.Section 1 and 2 presents the introduction and related works about QCA.In Section 3, the functioning procedure of QCA technology is succinctly presented.Sections 4 and 5 give about the reversible logic and proposed design of Toffoli gate and its implementation.In section 6, the simulation results were examined using a thorough comparison of the several properties of these suggested designs.Section 7 includes a summary of the suggested circuits and concludes with a discussion of future work.

QCA Terminology
The most basic unit of QCA is a cell with two additional electrons and two quantum dots.One quantum dot is placed in each corner of the square QCA cell, as shown in Fig. 1.QCA relies on the interaction between neighboring cells through Coulomb's force.The quantum wire is shown as a grid of quantum cells in Figure 2. Fig. 3(a) shows the inverter gate, while Fig. 3(b) shows the majority gate, as the two primary gates in QCA.Most QCA circuits are designed using these gates.The logical formulation for a majority gate is M(A,B,C)=AB+BC+AC.Two-input logic "OR" and "AND" gates are made by polarizing one input of the majority gate to (P=+1) or (P=-1), respectively [15][16][17][18].Fig. 4 shows the various crossover techniiques in QCA.Four-step synchronization offers synchrony.As shown in Fig. 5, the circuit is divided into four clock zones, each of which has the "Switch," "Hold," "Release," and "Relax" phases.Signal propagation across QCA wire, which is made up of a series of QCA cells, is comparable to that through a traditional shift register [19].The system can easily compute both forward and backward thanks to the reversibility of the logic used.A reversible computation is one that can be started at any time in the past, stopped in the middle, and continued from any point in the final result.The following are the necessary and sufficient requirements for defining any reversible logic: There must be the same number of inputs and outputs, and all data is preserved via a one-to-one correspondence between them.
The Toffoli gate in reversible logic because of its importance to our investigation.Any reversible circuit may be used to generate a reversible variant of any conventional gate, since the Toffoli gate (also known as the CCNOT gate) is considered a universal gate.Figure 6 depicts the construction of a three-input XOR gate and a two-input XOR gate, as well as the proposed and QCA configuration.A reversible logic gate architecture based on a three-input and a two-input XOR gate is proposed in this research.Proposed Work QCA's majority gate is a versatile building block for many kinds of logic circuits.In this article, we detail the architecture of a Toffoli gate for a reversible 4-to-2 priority encoder.However, in addition to the majority gate, our Toffoli gate also includes a small QCA XOR gate.

Toffoli gate
XOR gates based on the cell-interaction theory are used to construct the minimal hardware overhead QCA priority encoder [12].There are five quantum states in a Toffoli gate.This logic gate takes in 3 inputs and outputs 3 values.Here's how the Toffoli gate works: In the absence of a one in the first two bits, the third bit remains unaltered; otherwise, it is inverted.As can be seen in Fig. 7, the inputs A, B, and C correspond to the corresponding outputs P, Q, and R of the Tofoli gate, which has the logic equation R=ABC, Q=B, and P=A.Toffoli gate, seen in Figure 7. Format symbolique and the proposed QCA Framework.The technique for implementing the Toffoli gate QCA seen in Fig. 7(a) is shown in Fig. 7(b).For testing and actual usage, use the QCADesigner tool.

Reversible Priority Encoder using Toffoli gate
A priority encoder is a device or process that reduces the number of binary outputs from a number of inputs.Priority encoders provide a binary representation, counting from zero, of the index of the most important active line.They are often used to manage interrupt requests because to their high priority response to interrupt input.When many components need the same resource, priority encoders are used to guarantee that the one with the greatest priority gets it.From the four input bits (I3, I2, I1, and I0), only two bits (Y1 and Y0) are generated by the 4-to-2 priority encoder.Here is the equation's formula: The simulation result for the suggested toffoli gate is shown in Fig. 8.As illustrated in Fig. 9, we have now connected the three Toffoli gates to create a 4-to-2 priority encoder.The suggested layout has six waste outlets.In Figure 10 you can see the planned QCA architectre.A reversible circuit's output will, of its own accord, generate trash.However, the useless outputs have another application in complex circuits.

Conclusion
This study proposes a 4-to-2 reversible priority encoder, a complex circuit building block consisting of three Toffoli gates.In order to create a 4-to-2 priority encoder, we employed a reversible Toffoli gate based on the TIEO (Three input EXOR gate).The suggested design uses fewer cells, less space, and fewer logic gates than the current one.Prior suggested implementations of reversible priority encoders in QCA have been studied.The best article [23][24] was selected for comparison with the proposed layout.Table I shows that compared to the referenced studies [23][24], the proposed arrangement requires fewer logic gates.The time it takes to complete a task is reduced as a consequence.The suggested designs for the Toffoli gate and the reversible 4-to-2 priority encoder, for example, make better use of the QCA logic gates than recent research [23,24] by an average of 87% and 82%, respectively.As can be shown in Table 1, the Toffoli gate QCA arrangement may also provide benefits in terms of cell count, area usage, and latency.When using the proposed strategy to optimize QCA circuits, the system is shown to benefit greatly.

Fig 5
Fig.4shows the various crossover techniiques in QCA.Four-step synchronization offers synchrony.As shown in Fig.5, the circuit is divided into four clock zones, each of which has the "Switch," "Hold," "Release," and "Relax" phases.Signal propagation across QCA wire, which is made up of a series of QCA cells, is comparable to that through a traditional shift register[19].Fig 5 Shows the various zones and phases in QCA clocking.

Fig. 11 .
Fig.11.The Simulation Result for the reversible proposed priority encoder

Table 1 .
Performance matrices for the proposed designs