E3S Web of Conferences

Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL

Rambabu Sanivarapu, Mallikarjuna Rao Y., Venkataiah C., Linga Murthy M.K., Laith H. Alzubaidi and Vyeshikha

E3S Web Conf., 391 (2023) 01184

Published online: 05 June 2023

DOI: 10.1051/e3sconf/202339101184

Rambabu Sanivarapu

Mallikarjuna Rao Y.

Venkataiah C.

Linga Murthy M.K.

Laith H. Alzubaidi

Vyeshikha

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