| Issue |
E3S Web Conf.
Volume 248, 2021
2021 3rd International Conference on Civil Architecture and Energy Science (CAES 2021)
|
|
|---|---|---|
| Article Number | 03032 | |
| Number of page(s) | 4 | |
| Section | Research on Civil Water Conservancy Engineering and Urban Architecture | |
| DOI | https://doi.org/10.1051/e3sconf/202124803032 | |
| Published online | 12 April 2021 | |
Design of domestic serial and parallel interface module
Jiangsu Automation Research Institute, Lianyungang, Jiangsu, 222000, China
* Corresponding author’s e-mail: sunchuanyu7@126.com
Domestic serial and parallel interface module is based on domestic high performance FPGA CPCIE module. This type of FPGA has rich logical resources and internal integration of a variety of high-speed interfaces, such as PCIE, high-speed Serdes interface, which can achieve serial port, time system, network and other interfaces design, greatly simplifying the hardware design of the module. The main communication interfaces, PCIE and UART, are realized by the IP core of FPGA, realizing the integration of the main functions on the chip, which greatly improves the flexibility and expansibility of the design.
© The Authors, published by EDP Sciences, 2021
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.
Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.
Initial download of the metrics may take a while.