High Power Self-Aligned, Trench-Implanted 4H-SiC JFETs

¹ IESL/ FORTH, Vassilika Vouton, PO Box 1385 Heraklion, Greece
² Grenoble-INP, IMEP-LAHC, F-38000 Grenoble, France

Email: vamvk@hotmail.com
Email: konstantinos.zekentes@imep.grenoble-inp.fr

Abstract

The process technology for the fabrication of 4H-SiC trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) has been developed. The optimized TIVJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. A source-pillars sidewall oxidation and subsequent removal of the metallization from the top of the sidewall oxide ensured isolation between gate and source. Optimum planarization of the source pillars top has been performed by cyclotene spin coating and etch back. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The voltage blocking exhibits a triode shape, which is typical for a static-induction transistor (SIT) operation. The transistors exhibited high ON current handling capabilities (Direct Current density >1kA/cm²) and values of R_ON ranging from 6 - 12 mΩ•cm² depending on the channel length. Maximum voltage blocking was 800V limited by the edge termination. The maximum voltage gain was 51. Most transistors were normally-on. Normally-off operation has been observed for transistors lower than 2μm channel width (mask level) and deep implantation.