Fault Mitigation in Seven-Level Diode Clamped with Static Switch Based Fourth Leg Inverter Topology for Induction Motor Drives

Dr. Vasupalli Manoj, Assistant Professor, Department of Electrical and Electronics Engineering, GMR Institute of Technology, Rajam, India – 532127, Vizianagaram, Andhra Pradesh .
Dr. R.S.R. Krishnam Naidu, Associate Professor, Department of Electrical and Electronics Engineering, NS Raju Institute of Technology, Sontyam, Visakhapatnam, India .
Dr. M. Ramasekhara Reddy, Assistant Professor, Department of EEE, JNTUA College of Engineering, Anantapur, Andhrapradesh, India-515002 .

^* Corresponding Author: manoj.v@gmrit.edu.in

Abstract

Modern day life demands the use of inverters at the point of utilization for many of the applications especially for motor drives used in industrial applications. Conventional inverters suffer from a setback of high harmonics at the output of inverter. Multilevel inverters produce stepped output nearer to sinusoidal reducing the harmonic distortion at the output. Faults are quite common in occurrence in inverters and needs to be identified and mitigated as quickly as possible. This paper presents seven-level diode clamped multi-level inverter topology with fourth leg for fault mitigation. Fourth leg is operated with thyristor based control and gets activated from the signals obtained from algorithm. An algorithm was given to identify the fault and send activating signals to fourth leg of inverter. Fault was internally generated only in phase-A in inverter circuits which can be applied the effectiveness of four-leg topology to phase-B and phase-C of inverter as like in phase-A. Simulation work was carried out and results were obtained using MATLAB/SIMULINK software.