Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL

^1,2 Department of Electronics & Communication Engineering, Santhiram Engineering College, Nandyal, Andhra Pradesh, 518501 INDIA
³ Department of Electronics & Communication Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, 518501 INDIA
⁴ Department of Electronics & Communication Engineering, LakiReddy Bali Reddy College of Engineering, Mylavaram, Andhra Pradesh, 518501 INDIA
⁵ The Islamic University, Faculty of Engineering, Najaf, Iraq
⁶ Uttaranchal School of Computing Sciences, Uttaranchal University, Dehradun, 248007 INDIA

^* Corresponding author: ramababu.ece@srecnandyal.edu.in

Abstract

Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic. Although this format claims to deliver more precise outcomes with the same bit width as ordinary floating point, the duration of the operation fluctuation during posit field identification poses a hardware design problem. The POSIT-based MAC Unit is created using Verilog HDL in this study, and the designed architecture is evaluated for good operation before being implemented on an FPGA using Xilinx Vivado.