E3S Web Conf.
Volume 391, 20234th International Conference on Design and Manufacturing Aspects for Sustainable Energy (ICMED-ICMPC 2023)
|Number of page(s)||11|
|Published online||05 June 2023|
Performance evaluation of SRAM design using different field effect transistors
1 Department of Electronics & Communication Engineering, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, Andhra Pradesh, 518501 INDIA
2 Department of Electronics & Communication Engineering, Santhiram Engineering College, Nandyal, Andhra Pradesh, 518501 INDIA
3 Department of Computer Science Engineering, SVR Engineering College, Nandyal, Andhra Pradesh, 518501 INDIA
4 Sr.Assistant Professor, ECE Department, Lakireddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna District - 521230, Andhra Pradesh, INDIA
5 The Islamic University, Faculty of Engineering, Najaf, Iraq
* Corresponding author: email@example.com
SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.
Key words: SRAM / CNTFET / DRAM / FINFET / GNRFET
© The Authors, published by EDP Sciences, 2023
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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