E3S Web Conf.
Volume 391, 20234th International Conference on Design and Manufacturing Aspects for Sustainable Energy (ICMED-ICMPC 2023)
|Number of page(s)
|05 June 2023
Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits
1 Rajeev Gandhi Memorial College of Engineering and Technology, Nandyal, India
2 Santhiram Engineering College, Nandyal, Andhra Pradesh - 518501, India
3 SVR Engineering College, Nandyal, Andhra Pradesh - 518501, India
4 Sr.Assistant Professor, ECE Department, Lakireddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna District - 521230, Andhra Pradesh, INDIA
5 The Islamic University,Faculty of Engineering, Najaf, Iraq
6 Uttaranchal School of Computing Sciences,Uttaranchal University, Dehradun 248007 INDIA
* Corresponding author: email@example.com
Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.
Key words: Carbon nano-tube field effect transistor (CNTFET) / Power consumption / Ternary logic circuits / Ternary adders and multipliers
© The Authors, published by EDP Sciences, 2023
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