Influence of Parasitic Inductances on Switching Performance of SiC MOSFET

¹ State Key Laboratory of Advanced Power Transmission Technology (Global Energy Interconnection Research Institute of State Grid Corporation of China), Beijing 102209, China
² State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources (North China Electric Power University), Beijing 102206, China

Abstract

Compared to the silicon power devices, silicon carbide device has shorter switch time. Hence, as a result of the faster transition of voltage (dv/dt) and current (di/dt) in SiC MOSFET, the influence of parasitic parameters on SiC MOSFET’s switching transient is more serious. This paper gives an experimental study of the influence of parasitic inductance on SiC MOSFET’s switching characteristics. Most significance parameters are the parasitic inductances of gate driver loop and power switching loop. These include the SiC MOSFET package’s parasitic inductance, interconnect inductance and the parasitic inductance of dc link PCB trace. This paper therefore focuses on analysis and comparison of different parasitic parameters under various operation conditions in terms of their effect on overvoltage, overcurrent and switching power loss.