| Issue |
E3S Web Conf.
Volume 391, 2023
4th International Conference on Design and Manufacturing Aspects for Sustainable Energy (ICMED-ICMPC 2023)
|
|
|---|---|---|
| Article Number | 01028 | |
| Number of page(s) | 7 | |
| DOI | https://doi.org/10.1051/e3sconf/202339101028 | |
| Published online | 05 June 2023 | |
ASIC Implementation of Bit Matrix Multiplier
Department of ECE, VNR Vignana Jyothi Institute of Engineering and Technology, Telangana, India
Corresponding Author: swethareddy_k@vnrvjiet.in
In computer science and digital electronics, a bit matrix multiplier (BMM) is a mathematical operation that is used to quickly multiply binary matrices. BMM is a basic component of many computer algorithms and is utilized in fields including machine learning, image processing, and cryptography. BMM creates a new matrix that represents the product of the two input matrices by performing logical AND and XOR operations on each matrix element’s binary value. BMM is a crucial method for large-scale matrix operations since it has a lower computational complexity than conventional matrix multiplication. Reduced computational complexity: When compared to conventional matrix multiplication algorithms, BMM has a lower computational complexity since it performs matrix multiplication using bitwise operations like logical AND and XOR. Faster processing speeds are the result, particularly for complex matrix computations. Less memory is needed to store the binary values of the matrices in BMM because these values can be expressed using Boolean logic. As a result, less memory is needed, and the resources can be used more effectively.
© The Authors, published by EDP Sciences, 2023
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