Performance Enhancement Counter with Minimal Clock Period

¹ PG Scholar, Department of Electronics and Communication Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamilnadu, India
² Associate Professor, Department of Electronics and Communication Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamilnadu, India

Abstract

A synchronous binary counter is a fundamental component in VLSI design which are used commonly. synchronous binary counter is fast and are used in many applications as it supports wide bit-width. Due to large fan-outs and long carry chains many previous counters have low counting rate when the size of the counters is large. A new fast structure has been suggested for synchronous binary counter with a very low delay for counter with size ranging from 8 to 128 bits. To reduce the complexity of hardware a 1-bit Johnson counter has been used and then duplicate it to minimise propagation delay induced by large fan-outs. The suggested design is realised with a small number of flip-flops, using a back carry propagation counter and a counter based on state look ahead logic, which reduces power and delay.