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Cited article:

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Venkataiah C., Mallikarjuna Rao Y., Manjula Jayamma, Rambabu S., Linga Murthy M.K., Laith H. Alzubaidi, Sanjay Mishra

E3S Web Conf., 391 (2023) 01221

Published online: 2023-06-05

DOI: https://doi.org/10.1051/e3sconf/202339101221

This article has been cited by the following article(s):

Comparative Analysis of Ternary Half Adder Using CNTFET

Journal on Electronic and Automation Engineering 4 (2 June 2025) 147 (2025)
https://doi.org/10.46632/jeae/4/2/22

Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits

Najibullah Fazeli, Mehdi Bekrani and Mohammadreza Fathollahi
Integration 104 102441 (2025)
https://doi.org/10.1016/j.vlsi.2025.102441