Performance Analysis Of SRAM and Dram in Low Power Application

¹ Department of Electronics And Communication Engineering, Prince shri Venkateshwara Padmavathy Engineering College, Chennai, India
² Department of Mechanical Engineering, IES College Of Technology, Bhopal, MP 462044 India
³ Tashkent State Pedagogical University, Tashkent, Uzbekistan
⁴ Assistant professor, Department of mechanical Engineering, K. Ramakrishnan college of technology, Tiruchirappalli

^* Corresponding author: yuvarajjs@gmail.com
research@iesbpl.ac.in
yokesys@gmail.com

Abstract

All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.