Area-Delay-Power-Efficient GDI Architecture Select Adder to Carry

¹ Assistant Professor, Department of ECE, Nehru Institute of Engineering and Technology, Coimbatore, India
² Professor & Head, Department of ECE, Hindusthan Institute of Technology, Coimbatore, India
³ Associate Professor, Department of ECE, Hindusthan Institute of Technology, Coimbatore, India
⁴ Associate Professor, Department of ECE, Sri Eshwar College of Engineering, Coimbatore, India
⁵ Assisatnt Professor, Department of ECE, Nandha Engineering College, Erode, India

Abstract

The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select Adder based on a Binary to Excess-I Converter (BEC) was utilised, which required fewer logic resources than a standard CSLA and was hence more energy efficient. The fact that these CSLAs reject one sum after the calculation, however, means that they are not more efficient. As a result, the delay was not significantly decreased. It is necessary to apply the reduced logic CSLA in order to overcome this challenge. However, by employing the Gate Diffusion Input (GDI) Technique, it is possible to achieve a lower delay than the previously suggested reduced logic CSLA. The suggested technique consumes less power and has a shorter propagation latency than existing techniques. In addition, the number of transistors necessary for the circuit was reduced by implementing this GDI-based CSLA. It is possible to create an efficient adder using this technique, as seen above.