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All issues Volume 616 (2025) E3S Web Conf., 616 (2025) 02005 References
Open Access
Issue
E3S Web Conf.
Volume 616, 2025
2nd International Conference on Renewable Energy, Green Computing and Sustainable Development (ICREGCSD 2025)
Article Number 02005
Number of page(s) 13
Section Green Computing
DOI https://doi.org/10.1051/e3sconf/202561602005
Published online 24 February 2025
  1. Hasan, M., Hossain, M.S., Siddique, A.H., Hossain, M., Zaman, H.U. and Islam, S., 2021. A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder. Microelectronics Journal, 109, p. 104992. [CrossRef] [Google Scholar]
  2. Kito, N. and Takagi, N., 2019. Concurrent error detectable carry select adder with easy testability. IEEE Transactions on computers, 68(7), pp. 1105–1110. [CrossRef] [Google Scholar]
  3. Nam, M., Choi, Y. and Cho, K., 2018. High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic. Microelectronics Journal, 79, pp. 70–78. [CrossRef] [Google Scholar]
  4. Munawar, M., Khan, T., Rehman, M., Shabbir, Z., Daniel, K., Sheraz, A. and Omer, M., 2020, March. Low power and high speed Dadda multiplier using carry select adder with binary to excess-1 converter. In 2020 International Conference on Emerging Trends in Smart Technologies (ICETST) (pp. 1–4). IEEE. [Google Scholar]
  5. Kandula, B.S., Kalluru, P.V. and Inty, S.P., 2021. Design of area efficient VLSI architecture for carry select adder using logic optimization technique. Computational Intelligence, 37(3), pp. 1155–1165. [CrossRef] [Google Scholar]
  6. Valinataj, M., Mohammadnezhad, A. and Nurmi, J., 2018. A low-cost high-speed self-checking carry select adder with multiple-fault detection. Microelectronics Journal, 81, pp. 16–27. [CrossRef] [Google Scholar]
  7. B. Anand and V. V. Teresa, “Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer,” Journal of Computational and Theoretical Nanoscience, vol. 14, no. 1, pp. 269–276, Jan. 2017, DOI: 10.1166/jctn.2017.6316 [CrossRef] [Google Scholar]
  8. Hebbar, A.R., Srivastava, P. and Joshi, V.K., 2018. Design of high speed carry select adder using modified parallel prefix adder. Procedia computer science, 143, pp. 317–324. [CrossRef] [Google Scholar]
  9. Sakthivel, R. and Ragunath, G., 2021. Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter. Journal of Ambient Intelligence and Humanized Computing, 12(5), pp. 5513–5524. [CrossRef] [Google Scholar]
  10. Musala, S., Neelam, A.K., Sreenivasulu V. B. and Vardhan, K.V., 2021. Concurrent error detectable and self- repairable carry select adder. International Journal of Electronics, pp. 1–19. [Google Scholar]
  11. You, H., Yuan, J., Tang, W. and Qiao, S., 2019. An energy and area efficient carry select adder with dual carry adder cell. Electronics, 8(10), p. 1129. [CrossRef] [Google Scholar]
  12. Premananda, B.S., Bajpai, A., Shakthivel, G. and Anurag, A.R., 2021. Low power add-one circuit IPGL based high speed square root carry select adder. Indian Journal of Science and Technology, 14(9), pp. 776–786. [CrossRef] [Google Scholar]
  13. Jhamb, M., 2021. Low Power and Highly Reliable 8-Bit Carry Select Adder. In Innovations in Electrical and Electronic Engineering (pp. 537–549). Springer, Singapore. [Google Scholar]
  14. Valsalan, P. and Manimegalai, P., 2018. Intend of power-delay optimized Kogge-Stone based Carry Select Adder. ARPN Journal of Engineering and Applied Sciences. [Google Scholar]
  15. VijeyaKumar, K.N., Lakshmanan, M., Sakthisudhan, K., Saravanakumar, N., Mythili, R. and KamatchiKannan, V., 2022. Design and Implementation of High-Speed Energy-Efficient Carry Select Adder for Image Processing Applications. In Innovative Data Communication Technologies and Application (pp. 679–686). Springer, Singapore. [CrossRef] [Google Scholar]
  16. K. Kalpana., Dr.B. Paulchamy “An Efficient Architecture of Vedic Multiplier Using FINFET based Pass Transistor Logic”, International Journal of Engineering and Advanced technology (IJEAT), Volume 9, Issue 03, February 2020, Page: 2605–2611. [CrossRef] [Google Scholar]
  17. Penchalaiah, U. and Kumar, V.S., 2018. Survey: performance analysis of FIR filter design using modified truncation multiplier with SQRT based carry select adder. International Journal of Engineering & Technology, spc, 7(2.32), pp. 23–34. [Google Scholar]
  18. Sireesha, P., Kumar, G.R., Bhargavi, C.P., Sowjanya, A. and Rao, P.M., 2021, May. Design and analysis of 32 bit high speed carry select adder. In Journal of Physics: Conference Series (Vol. 1916, No. 1, p. 012006). IOP Publishing. [CrossRef] [Google Scholar]
  19. Hossain, M.S. and Arifin, F., 2021. Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder. AIUB Journal of Science and Engineering (AJSE), 20(2), pp. 1–7. [CrossRef] [Google Scholar]
  20. J. Dhanasekar, Gurunathan, V., Sathiyapriya, T., Dr.V.V. Teresa, Gurunathan, V., Sathiyapriya, T., Published A Paper Titled, “Design of Low Power 4-Bit Carry Look Ahead Adder Using Self Resetting and Gate Diffusion Input Logics” Solid State Technology Volume: 63 Issue: 6 Publication Year: 2020. [Google Scholar]
  21. V. V. Teresa, J. Dhanasekar, V. Gurunathan, and T. Sathiyapriya, “An Efficient Technique for Image Compression and Quality Retrieval in Diagnosis of Brain Tumour Hyper Spectral Image,” Machine Learning and Deep Learning Techniques for Medical Science, pp. 27–44, Mar. 2022, DOI: 10.1201/9781003217497-2 [CrossRef] [Google Scholar]
  22. V.V. Teresa, J. Dhanasekar, V. Gurunathan, T. Sathiyapriya, Published a book chapter titled, “An Efficient Technique for Image Compression and Quality Retrieval in Diagnosis of Brain Tumour Hyper Spectral Image”, in Machine Learning and Deep Learning Techniques for Medical Science, CRC Press on 12.05.2022. [Google Scholar]
  23. Prasanth Thiruvenkatam, T. Prabu, Krishnasamy Balasubramanian, Sridhar Sekar, Published a paper titled, “Video surveillance system-based human activity recognition using hierarchical auto-associative polynomial convolutional neural network with garra rufa fish optimization”, in International Journal of Pattern Recognition and Artificial Intelligence 2024. [Google Scholar]
  24. Prabu, T., & Srinivasan, K. (2024), “Design and Implementation of High-Performance FPGA Accelerator for Non-Separable Discrete Fourier Transform Optimizing Real-Time Image and Video Processing”, Journal of Nanoelectronics and Optoelectronics, vol. 19, no. 8, pp. 843–856 [CrossRef] [Google Scholar]

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