| Issue |
E3S Web of Conf.
Volume 540, 2024
1st International Conference on Power and Energy Systems (ICPES 2023)
|
|
|---|---|---|
| Article Number | 14001 | |
| Number of page(s) | 13 | |
| Section | VLSI, Artificial Intelligence and Physics | |
| DOI | https://doi.org/10.1051/e3sconf/202454014001 | |
| Published online | 21 June 2024 | |
Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis
1 Associate Professor, Dept. of ECE, G. Pullaiah College of Engineering and Technology, India-518002, Kurnool, Andhra Pradesh
2 UG Student, Dept. of ECE, G. Pullaiah College of Engineering and Technology, India-518002, Kurnool, Andhra Pradesh
* Corresponding Author: obulesub@gmail.com
One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the data before connecting into the bus line. This procedure reduces the crosstalk issue by using the improved logic architecture. The proposed approach utilizes a combination of circuit-level optimization techniques, such as gate sizing and interconnect optimization, and advanced timing analysis tools to minimize power consumption and reduce crosstalk.
Key words: Crosstalk / Static timing analysis / Bus encoder / Bus decoder,Very Large Scale integrated (VLSI)Circuit / Crosstalk probability detector
© The Authors, published by EDP Sciences, 2024
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