EDP Sciences logo
Web of Conferences logo
Search
Menu
All issues Volume 391 (2023) E3S Web Conf., 391 (2023) 01220 References
Open Access
Issue
E3S Web Conf.
Volume 391, 2023
4th International Conference on Design and Manufacturing Aspects for Sustainable Energy (ICMED-ICMPC 2023)
Article Number 01220
Number of page(s) 13
DOI https://doi.org/10.1051/e3sconf/202339101220
Published online 05 June 2023
  1. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Circuit compatible modeling of carbon nanotube FET’s in the ballistic limit of performance,” Proc. 3rd IEEE Conf. Nanotechnology, 12-14, 343–346, Aug. (2003). [CrossRef] [Google Scholar]
  2. C. Venkataiah, M. Tejaswi “A Comparative Study of Interconnect Circuit Techniques for Energy Efficient on-Chip Interconnects” Int Jour of Comp App. 0975 - 8887, 109 January (2015). [Google Scholar]
  3. J. Deng, H. Wong, “A Compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part i: model of the intrinsic channel region,” IEEE Trans. Elect Dev, 54, 3186–3194 (2007). [CrossRef] [Google Scholar]
  4. C. Venkataiah, K. Satya Prasad, T. Jaya Chandra Prasad “Effect of Interconnect parasitic variations on circuit performance parameters” IEEE Int conf on Comm and Elect Sys (ICCES), Coimbatore, India, October, (2016). [Google Scholar]
  5. J. Deng, H. Wong, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - part ii: full device model and circuit performance benchmarking,” IEEE Trans. Electron Devices, 54, 3195–3205 (2007). [CrossRef] [Google Scholar]
  6. Karthik Rao, R., Bobba, P.B., Suresh Kumar, T., Kosaraju, S., Feasibility analysis of different conducting and insulation materials used in laminated busbars, Materials Today: Proceedings, 2019, 26, pp. 3085–3089. [Google Scholar]
  7. Sheng Lin, Yong-Bin Kim, F. Lombardi, “A novel CNTFET based ternary logic gate design,” Proc. IEEE Int. Midwest Symp. Circuits and Systems, Cancun, Mexico, 435–438, August (2009). [Google Scholar]
  8. C. Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Crosstalk induced performance analysis of single walled carbon nanotube interconnects using stable finite difference time domain model”, Jour of nanoelect and optoelect. 12, 1–10 (2017). [CrossRef] [Google Scholar]
  9. C. Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects”, Jour of Comp Elect, Springer, June, (2018). [Google Scholar]
  10. Sheng Lin, Yong-Bin Kim, F. Lombardi, “CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits,” IEEE Transactions on Nanotechnology, 10, 217–225, March (2011). [CrossRef] [Google Scholar]
  11. C. Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Insertion of optimal number of repeaters in pipelined nano interconnects for transient delay minimization”, Cir sys and Sig Proc, Springer, June, (2018). [Google Scholar]
  12. Tummala, S.K., Indira Priyadarshini, T., Morphological Operations and Histogram Analysis of SEM Images using Python, Indian Journal of Engineering and Materials Sciences, 2022, 29(6), pp. 794–798 [Google Scholar]
  13. M. H. Moaiyeri, R. F. Mirzaee, A. Doostaregan, K. Navi, O. Hashemipour, “A universal method for designing low-power carbon nanotube FET-based multiplevalued logic circuits,” IET Comput. Digit. Tech., 7, 167–181 (2013). [CrossRef] [Google Scholar]
  14. C. Venkataiah, K. Satyaprasad, T. Jayachandra Prasad, “Signal integrity analysis for coupled SWCNT interconnects using stable recursive algorithm”, Microelectronics Journal, 74, 13–23 (2018). [CrossRef] [Google Scholar]
  15. Xinran Wang and Yi Shi, “Fabrication Techniques of Graphene Nanostructures,” (2014). [Google Scholar]
  16. Suresh Kumar Tummala, Phaneendra Babu Bobba & Kosaraju Satyanarayana (2022) SEM & EDAX analysis of super capacitor, Advances in Materials and Processing Technologies, 8:sup4, 2398–2409 [CrossRef] [Google Scholar]
  17. Ying-Yu Chen, Amit Sangai, A. Rogachev, M. Gholipour, G. Iannaccone, G. Fioriand D. Chen, “A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation,” IEEE Trans on Nanotech, 14, 1068–1082. Aug (2015). [CrossRef] [Google Scholar]
  18. M. Gholipour, Ying-Yu Chen, Amit Sangai, and D. Chen “Highly Accurate SPICECompatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling,” Design, Automation and Test in Europe Conference and Exhibition, (2014). [Google Scholar]
  19. Chang, H. and Wu, H. (2013), Graphene Based Nanomaterials: Synthesis, Properties, and Optical and Optoelectronic Applications. Adv. Funct. Mater., 23: (1984-1997). [Google Scholar]
  20. A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. [Google Scholar]
  21. Davu, S.R., Tejavathu, R. & Tummala, S.K. EDAX analysis of poly crystalline solar cell with silicon nitride coating. Int J Interact Des Manuf (2022). [Google Scholar]
  22. Lundstrom, and H. Dai, “High-k Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates,” Nature Materials, 1, 241–246 (2002). [CrossRef] [PubMed] [Google Scholar]
  23. S. L. Hurst, “Multiple-valued logic—its status and its future,” IEEE Trans. Comput, C-33, 1160–1179, Dec. (1984). [CrossRef] [Google Scholar]
  24. J. Srinivas Rao, Suresh Kumar Tummala, Narasimha Raju Kuthuri, Comparative investigation of 15 Level and 17 level cascaded h-bridge MLI with cross h-bridge MLI fed permanent magnet synchronous motor, Indonesian Journal of Electrical Engineering and Computer Science, 21(2), pp. 723–734, (2020) [Google Scholar]
  25. A. Raychowdhury, K. Roy, “Carbon-nanotube-based voltage mode multiple-valued logic design,” IIEEE Trans. on Nanotechnology, 4, 168–179, March (2005). [CrossRef] [Google Scholar]
  26. Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo, and Manasi Muglikar, [Google Scholar]
  27. “High-Performance Ternary Adder Using CNTFET,” IEEE transactions on nanotechnology, 16, May(2017). [Google Scholar]
  28. Tummala, S.K., Kosaraju, S. & Bobba, P.B. Optimized power generation in solar using carbon substrate for reduced greenhouse gas effect. Appl Nanosci 12, 1537–1543 (2022) [CrossRef] [Google Scholar]
  29. C. Venkataiah, V.N.V. Satya Prakash, K. Mallikarjuna and T. Jayachandra Prasad, “Investigating the effect of chirality, oxide thickness,temperature and channel length variation on a threshold voltage of MOSFET, GNRFET, and CNTFET”, Jour of mech of contand maths sci, 232–244, September, (2019). [Google Scholar]
  30. Vijay Rao Kumbhare, Punya Prasanna Paltani, C. Venkataiah, and Manoj Kumar Majumder “Analytical Study of Bundled MWCNT and Edged-MLGNR Interconnects: Impact on Propagation Delay and Area”, IEEE Trans on Nanotech, 18, 606–610, June, (2019). [CrossRef] [Google Scholar]
  31. Jinghang Liang, Linbin Chen, Jie Han and Fabrizio Lombardi, “Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-type Carbon Nanotube FETs,” IEEE transactions on nanotech, 13, July (2014). [Google Scholar]
  32. Chetan Vudadha, M. B. Srinivas “Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETS” IEEE transactions on nanotech, 17, July (2018). [Google Scholar]

Current usage metrics show cumulative count of Article Views (full-text article views including HTML views, PDF and ePub downloads, according to the available data) and Abstracts Views on Vision4Press platform.

Data correspond to usage on the plateform after 2015. The current usage metrics is available 48-96 hours after online publication and is updated daily on week days.

Initial download of the metrics may take a while.